Process for adjusting data structures of a floorplan upon...

Details Process for adjusting data structures of a floorplan upon... Process for adjusting data structures of a floorplan upon...

2006-10-10

2006-10-10

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07120892

ABSTRACT:
A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that plbock, identifies other pblocks nested within it and contains at least a list of boundary pins for that pblock.

REFERENCES:
patent: 5140526 (1992-08-01), McDermith et al.
patent: 5499191 (1996-03-01), Young
patent: 5513119 (1996-04-01), Moore et al.
patent: 5617327 (1997-04-01), Duncan
patent: 6009251 (1999-12-01), Ho et al.
patent: 6145117 (2000-11-01), Eng
patent: 6170080 (2001-01-01), Ginetti et al.
patent: 6408422 (2002-06-01), Hwang et al.
patent: 6631508 (2003-10-01), Williams
patent: 6845494 (2005-01-01), Burks et al.
patent: 2004/0078767 (2004-04-01), Burks et al.
U.S. Appl. No. 10/792,164, filed Mar. 3, 2004, Knol et al.
U.S. Appl. No. 10/800,042, filed Mar. 12, 2004, Knol et al.
U.S. Appl. No. 10/892,612, filed Jul. 16, 2004, Knol et al.
Wang, Maogang, et al., “Multi-Million Gate FPGA Physical Design Challenges,” ICCAD '03, Nov. 11-13, 2003, pp. 891-898, Available from ICCAD, San Jose, California, USA.

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