Process for 3D chip stacking

Details Process for 3D chip stacking Process for 3D chip stacking

1996-10-28

1998-11-10

Duda, Kathleen

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

430314, 430945, 438109, 438612, 438618, 438666, G03F 700, H01L 2160

Patent

active

058341625

ABSTRACT:
A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

REFERENCES:
patent: 4778326 (1988-10-01), Atlhouse et al.
patent: 5107586 (1992-04-01), Eichelberger et al.
patent: 5126286 (1992-06-01), Chance
patent: 5571754 (1996-11-01), Bertin et al.
patent: 5653019 (1997-08-01), Bernhardt et al.

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