Process flow to reduce spacer undercut phenomena

Details Process flow to reduce spacer undercut phenomena Process flow to reduce spacer undercut phenomena

2001-12-20

2002-09-10

Christianson, Keith (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S305000, C438S761000, C438S568000

Reexamination Certificate

active

06448167

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form, and retain during subsequent processing steps, a composite insulator spacer located on the sides of a gate structure.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has resulted in improved device performance as well as decreases in processing costs. Smaller device features allow reductions in performance degrading parasitic junction capacitances to be realized. In addition a greater number of smaller semiconductor chips comprised with sub-micron features, but still exhibiting device densities equal to, or greater than, counterpart semiconductor chips fabricated with larger features, can be obtained from a specific size starting substrate thus reducing the processing cost for an individual semiconductor chip. However the trend to micro-miniaturization can place stringent demands on specific semiconductor elements. For example for sub-0.13 um technology the insulator spacer formed on the sides of a gate structure can be less than 700 Angstroms in thickness. The use of silicon oxide as a component of an insulator spacer, as well as the number of times during a process a semiconductor device is subjected to an hydrofluoric (HF), containing wet clean procedure, can result in undesired thinning of the silicon oxide spacer, or if silicon oxide is employed as an underlying layer of a composite insulator spacer, severe undercutting of the silicon oxide insulator spacer component. The undercut, silicon oxide spacer, subsequently filled with metal silicide, can result in yield loss due to gate to substrate shorts or leakage.
This invention will teach a process flow in which a thin, chemically vapor deposited (CVD), silicon oxide layer can be employed as an underlying layer for a composite insulator spacer as a result of a densification procedure performed to the silicon oxide component, allowing the removal rate of densified silicon oxide, in a HF type solution, to be reduced. The densified silicon oxide spacer component thus can survive exposures to HF containing wet etch clean procedures, C with a reduced amount of undercut when compared to counterparts formed with non-densified silicon oxide spacer components, thus reducing the risk of gate to substrate shorts or leakage. Prior art such as Das et al, in U.S. Pat. No. 6,113,128, as well as Thei et al, in U.S. Pat. No. 6,265,271, describe anneal procedures performed on silicon oxide layers, however these prior arts, do not describe the process sequence taught in this present invention, in which a specific process sequence is employed for densification of a silicon oxide spacer component, at a specific point of the process, prior to a series of wet clean procedures, performed using IF type solutions.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a metal oxide semiconductor field effect transistor (MOSFET), device, featuring a composite insulator spacer, formed on the sides of a gate structure.
It is another object of this invention to form a composite insulator spacer comprised of a thin, underlying, CVD silicon oxide component, obtained using tetraethylorthosilicate (TEOS), as a source, a silicon nitride component, and an overlying, CVD silicon oxide component, again obtained using TEOS as a source.
It is still another object of this invention to subject the thin, underlying CVD silicon oxide layer, used to define a subsequent component of the composite insulator spacer, to an anneal procedure, prior to deposition of the silicon nitride layer, for purposes of densification, reducing the removal rate of the silicon oxide component in subsequent HF wet clean procedures.
In accordance with the present invention a method of densifing an underlying silicon oxide component of a composite insulator spacer, located on the sides of a gate structure, to reduce the extent of undercut of the underlying silicon oxide component during subsequent wet clean procedures is described. After formation of a gate structure on an underlying gate insulator layer, ions to be used for a lightly doped source/drain (LDD), region, are implanted in an area of a semiconductor substrate not covered by the gate structure A first silicon oxide layer is deposited, using TEOS as a source. A rapid thermal anneal (RTA) procedure is next used to density the first silicon oxide layer, resulting in a reduced removal rate for the densified silicon oxide layer, in HF containing solutions, when compared to undensified, TEOS deposited, silicon oxide counterparts. In addition the RTA procedure activates the implanted ions forming the lightly doped source/drain region. A silicon nitride layer is then deposited, followed by deposition of an overlying, overlying silicon oxide layer, again using TEOS as a source. An anisotropic, reactive ion etching (RIE), procedure is used to selectively form the initial composite spacer in the overlying, second silicon oxide layer, and in the silicon nitride layer, with the RIE procedure terminating at the appearance of the underlying, first silicon oxide layer. A first HF containing, wet etch procedure is employed to remove the portions of underlying, first silicon oxide layer, not covered by the initial composite spacer, resulting in the final composite spacer. After implantation of ions needed for a heavily doped source/drain region, in an area not covered by the gate structure or by the final composite insulator spacer, a resistor protect oxide (RPO) layer, is deposited followed by an anneal procedure used to activate the implanted ions, resulting in formation of the heavily doped source/drain region. Removal of the RPO layer is accomplished using another HF containing solution, followed by a pre-metal wet clean procedure, performed again in an HF containing solution. The extent of the undercut of underlying, first silicon oxide layer, exposed at the edge of the final composite insulator spacer during the HF cleans, is minimized as a result of the previously performed RTA, densification procedure. Metal silicide formation is then accomplished on the top surface of the gate structure, and on the heavily doped source/drain region.


REFERENCES:
patent: 6153483 (2000-11-01), Yeh et al.

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