Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
1998-07-02
2002-05-28
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S007000, C438S014000, C438S015000, C438S460000, C356S237600
Reexamination Certificate
active
06395567
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a defect identification and classification methodology. More specifically, this invention relates to a defect identification and classification methodology that detects nonrandom defects. Even more specifically, this invention relates to a defect identification and classification methodology that detects uniformly induced defects.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on a semiconductor integrated circuit chip. Another part of reducing the cost of a semiconductor integrated circuit chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die or dice) from each wafer is not 100% because of defects during the manufacturing process. The number of good die obtained from a wafer determines the yield. As can be appreciated, die that must be discarded because of a defect or defects increases the cost of the remaining usable die because the cost of processing the wafer must be amortized over the usable die.
A single semiconductor die requires numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor die are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to rapidly identify and classify the defects on a layer of a semiconductor chip is an invaluable aid to those involved in research and development, process, problem solving and failure analysis of integrated circuits.
One current method by which defects are rapidly detected and evaluated, is to employ a wafer scanning system which uses an optical site-to-site comparison technique to determine if a difference exists or if differences exist between adjacent dice. If a difference exists, the location of that difference is noted and is marked as a defect. To perform this task, the system scans a “swath” of a predetermined height across the surface of a wafer from one side to the opposite side and back. The scanning of swaths across the wafer is continued until the entire wafer is scanned or until a predetermined number of defects have been detected. This technique is valuable in determining if random defects occur, but is inadequate if the entire wafer is affected uniformly with induced defects, such as very wide or narrow CDs, over or under etch conditions (pitting, color variation) and unstripped resist.
Therefore, what is needed is a system in which optical data from an “ideal” die can be stored and used as a pre-scan condition that compares the optical data from the ideal die to optical data from die on production wafers.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained by a method of detecting defects on a semiconductor wafer wherein scanned data from each dice on a processed layer on a semiconductor wafer is compared to data from an ideal dice obtained from the same layer on a pre-production wafer.
In another aspect of the invention, the scanned data is obtained by an optical scanning system.
The described method thus provides a method in which complete wafer level information can be obtained without impacting manufacturing throughput, allows for monitoring uniformly distributed process problems, enables monitoring process variations over time, allows monitoring process integrity on a macro as well as on a micro level and allows monitoring of process drift in individual equipment, evolution as will as abrupt change.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5943551 (1999-08-01), Schemmel et al.
patent: 6011619 (2000-01-01), Steffan et al.
patent: 6017771 (2000-01-01), Yang et al.
Huang et al., Wafer Testing with Pairwise Comparisons, pp. 374-383, (IEEE), 1992.*
Kondo et al., A real time Process Control System for IC Testing, pp. 331-338, (IEEE), 1991.*
Huang et al., A Diagnosis Algorithm for Constant Degree Structures and Its Application to VLSI Circuit Testing, pp. 363-372, (IEEE), 1995.
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Brairton Scott
Nelson H. Donald
Pham Long
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