Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-07-05
2005-07-05
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S727000
Reexamination Certificate
active
06915495
ABSTRACT:
Management of Test Access Port functions of a plurality of components arranged on a single chip by selectively driving the TAP function of each of the components with respective clocks, whilst the further signals for driving the TAP function are used in a shared mode among the various components. Preferably, associated with the aforesaid clocks is a pull-down function for selectively blanking the respective clocks in conditions of non-use. In a preferred way, the aforesaid dedicated clocks are generated on board the chip.
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Whetsel, L., “An IEEE 1149.1 Based Test Access Architecture For ICs with Embedded Cores,”International Test Conference, New York, Nov. 1, 1997, pp. 69-78.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Tarleton E. Russell
Thompson A. M.
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