Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-31
2002-08-06
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06430729
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to identifying parasitic values of devices
etworks making up integrated circuits and more particularly to a process and system for maintaining a 3 sigma process tolerance for parasitic extraction with on-the-fly biasing.
2. Description of the Related Art
When integrated circuits are designed, various competing goals must be balanced to achieve a circuit which performs as desired. One such goal is the control of parasitic parameters. For example, coupling capacitances, load capacitances, and wire RC delays are common parasitic parameters. Conventionally, designers prepare a model of an integrated circuit. The model traditionally includes devices such as transistors, capacitors, logic devices, etc. connected by wiring. The parasitic parameters of the devices and the wiring is determined or estimated from previous empirical testing.
In addition, the integrated circuit designer must take into account that the manufacturing process will produce variations (e.g., because of inconsistent processing TEMPERATURE, processing time and material usage) that change the shape, thickness, DENSITY, etc. of the devices and wiring within the integrated circuit design. Therefore, designers accommodate for potential manufacturing process variations by ensuring the circuit will perform as desired within the limits of the manufacturing process variations. Parasitic capacitance and resistance within VLSI (very large scale integration) circuits are calculated using the shapes of the design to determine the horizontal dimensions and the process description for the vertical dimensions. All horizontal dimensions are biased to allow for horizontal shifts during the process, trapezoidal cross-sections and further shifts of the actual physical geometry from the design data caused by manufacturing variations. These biases are different for resistance calculations and capacitance calculations due to variations in the resistivity and dielectric constant within the thickness of the conductor layers.
However, conventional systems suffer from the drawback that only the theoretical maximum and minimum variances within the manufacturing process are considered when performing integrated circuit design. Therefore, conventional systems are designed for potentially unrealistic parasitic values, which limits the designer's ability to efficiently utilize the size of devices and wiring within the integrated circuit design.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters impacting devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices based on the manufacturing process parameters, combining the parasitic performance distribution for each of the devices into a net parasitic value, and forming a parameterized model based on the net parasitic values.
The calculating of the parasitic performance distribution includes simultaneously calculating a range of parasitic values for each of the devices based on the manufacturing process parameters. The range of values includes a best case parasitic value, a worst case parasitic value and a nominal parasitic value. The process also includes deriving parasitic performance values for the devices for the best case parasitic value, the worst case parasitic value and the nominal parasitic value from the parameterized model. The manufacturing process parameters include also different overlay conditions.
The parasitic performance distribution is maintained within a predetermined accuracy range such that the net parasitic value is within the accuracy range. The manufacturing process parameters include a size and spacing of wiring and insulation within layers of the integrated circuit.
The invention described below overcomes these difficulties with a novel system and method which maintains a 3 sigma process tolerance for parasitic extraction. To utilize conventional extraction programs geometric description of the system of conductors and devices is performed at least three times, describing a best case extreme, the nominal design point and a worst case extreme situation. Three extraction runs and three timing evaluations have to be performed. The invention described below allows the same and even more information with one extraction run, gaining a significant performance advantage.
The invention described below also extracts netlists in form of parameterized models for the parasitic elements. This allows the timing tool not only to consider the three situations for which the geometry of the conductors and wires was created, but also all situations in between. Also multiple runs are possible to statistically evaluate all possible combinations of parasitic values with ‘Monte Carlo’ techniques. Conventional methods do not allow this.
Furthermore, this invention includes a method to account for overlay tolerances in extraction. Overlay variations cause two or more levels to be shifted towards each other, which destroy the symmetry in symmetrically laid out devices. This lack of symmetry impacts stability in storage cells and other circuits which rely on equal devices. The ability to evaluate the loss of divice symmetry due to overlay shifts is also a new feature not described in other extraction tools.
REFERENCES:
patent: 5901063 (1999-05-01), Chang
Dewey L. William
Habitz Peter A.
McCullen Judith H.
Seibert Edward W.
Do Thuan
International Business Machines - Corporation
Kotulak, Esq. Richard M.
McGinn & Gibb PLLC
Smith Matthew
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