Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
1998-10-19
2001-03-13
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C341S100000, C341S101000, C341S106000, C358S001180
Reexamination Certificate
active
06202108
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION;
The present invention relates to a process for initializing a serial link between two integrated circuits comprising a parallel-serial and serial-parallel port, two ports have been previously initialized, and the device which allows the process to be implemented.
SUMMARY OF THE INVENTION
As shown in
FIGS. 1A
,
1
B,
2
A, and
2
B, the device of the present invention is used in an information processing system which comprises two identical circuits (
1
), a main memory (
12
a
) and a shared extended memory (
12
c
). The first circuit is the master, the second circuit is the slave, and each circuit comprises at least one parallel/serial port. All ports (
10
) of each integrated circuit are identical.
The first object of the invention is achieved because; The process for initializing a serial link between two integrated circuits comprising an input-output port between a parallel bus and a serial link, this port using two clocks with different frequencies, a first high-frequency clock for the serial link, called a transmitting and receiving clock CKT/CKR, and a second lower-frequency clock for the signals arriving from the parallel bus of the system (CKS), is characterized in that it comprises the following steps:
reinitialization of the port with isolation of the receiving clock logic;
reinitialization of the transmitting clock logic (CKT) (parallel-serial);
reset-to-zero of the serial link between the two ports. According to another characteristic, the step for reinitializing the port comprises:
a step in which the microprocessor associated with the port to be reinitialized sends a series of neutral messages which allow a receiving delay line (LLR) to be calibrated to these neutral messages and to extract from them a receiving clock signal (CKR), then to send a signal (CAL) indicating that the receiving clock has been calibrated.
According to another characteristic, the microprocessor associated with the integrated circuit disconnects the parallel port, sending no data to the parallel bus that links it to this port;
the integrated circuit deactivates each of its serial outputs and sends a 0-volt signal, possibly mixed with noise;
the integrated circuit sets its token counter to zero in order to avoid sending messages and reinitializes all its pointers.
According to another characteristic, each of the preceding steps is repeated in each of the ports of each of the circuits connected by the serial link.
According to another characteristic, the steps for initializing the ports are followed by a step for initializing serial communication (MM).
According to another characteristic, this step for initializing serial communication comprises:
a step for establishing the master/slave link;
a step for establishing the slave/master link;
a step for connecting the parallel bus to the port of the master circuit;
a step for connecting the parallel bus to the port of the slave circuit.
According to another characteristic, the step for establishing the master/slave link comprises:
a step in which the processor of the card of the master circuit sets an input (OE) of the port to a value 1 and transmits a continuous flow of null characters;
a step for calibrating the receiving clock (CKR) of the port of the slave circuit; and
a step for sending an interrupt to the microprocessor associated with the slave circuit;
a step for reinitializing the receiving clock logic of the slave circuit and sending two dummy messages to the receiving buffers of the port of the slave circuit;
a step for setting an input (OE) of the port of the slave circuit to the value 1; and
a step for transmitting null characters for a sufficient length of time determined by a periodic sampling signal of the slave port.
According to another characteristic, the step for establishing the slave/master link comprises:
a step for calibrating the receiving clock (CKR) of the port of the master circuit and for setting the calibration signal of this port to the valve
1
;
a step for sending an interrupt to the microprocessor associated with this master circuit;
a step for reinitializing the receiving clock logic of the port of this master circuit and for loading two dummy messages into the receiving buffers of the master circuit.
According to another characteristic, the step for connecting the parallel bus to the port comprises:
a step during which the microprocessor associated with the master circuit connects its parallel bus to the port of the master circuit;
a step for reading the dummy messages sent previously and for sending two tokens to the port of the slave circuit;
a step for the reception of the two tokens by the slave circuit; and
a step for the sending by the latter of an interrupt to the associated microprocessor associated with the master circuit;
a step for connecting the parallel bus of the associated microprocessor to the slave circuit;
a step for reading the dummy messages; and
a step for sending two tokens to the master circuit.
According to another characteristic, the tokens are generated by an operation for reading the dummy messages stored in the buffers (RCBUF) of the master port and slave port, respectively.
According to another characteristic, the detection of a calibration loss in either of the ports or a command for reinitializing the link triggers the following series of steps:
a step for isolating the receiving clock logic;
a step for deactivating the signal OE which, for the circuit having detected the calibration loss, results in the interruption of data transmissions to the remote receiving circuit;
a step for the detection of the calibration loss by the port of the remote receiving circuit; and
a step for starting the procedure for isolating the receiving clock logic of this circuit.
Another object of the invention is a device which allows the process to be implemented.
This second object is achieved because of the fact that the device which allows the implementation of the process for initializing a serial link between two integrated circuits comprising an input-output port between a parallel bus and a serial link, this port using two clocks with different frequencies, a first higher-frequency clock for the serial link, called a transmitting/receiving clock, and a second lower-frequency clock for the signals arriving from the parallel bus, called a system clock or a low-frequency clock, is characterized in that it comprises:
means for reinitializing the port with isolation of the is, receiving clock logic;
means for reinitializing the transmitting clock logic;
means for resetting the serial link between the two ports to zero.
According to another characteristic, the device comprises means which allow the microprocessor associated with the port to be reinitialized to send a series of neutral messages which allow a receiving delay line to be calibrated to these neutral messages and to extract from them a receiving clock signal, then to send a signal indicating that the receiving clock has been calibrated.
According to another characteristic, the device comprises:
means allowing the microprocessor associated with the integrated circuit to disconnect the port, sending no data to the parallel bus that links it to this port;
means allowing the integrated circuit to deactivate its outputs and to send a 0-volt signal, possibly mixed with noise;
means allowing the integrated circuit to set its token counter to zero in order to avoid sending messages and to reinitialize all its pointers.
According to another characteristic, the device comprises means which make it possible to repeat each of the steps of the process in each of the ports of each of the circuits connected by the serial link.
According to another characteristic, the device comprises means which make it possible to follow the steps for initializing the ports with a step for initializing serial communication.
According to another characteristic, the device comprises:
means for establishing the master/slave link;
means for establishing the slave/master link;
means for connecting the parallel bus to the
Autechaud Jean-François
Dionet Christophe
Bull S.A.
Elamin Abdelmoniem
Kondracki Edward J.
Lee Thomas C.
Miles & Stockbridge P.C.
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