Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-02-15
2005-02-15
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S116000, C716S030000
Reexamination Certificate
active
06857113
ABSTRACT:
A method and system of identifying one or more nets in a digital IC design that are at risk of electromigration comprises selecting a manufacturing process for the digital IC design and obtaining a clock period and process voltage. A voltage waveform transition time and effective capacitance is calculated for one or more of the nets. A maximum allowable effective capacitance for each one of the nets is calculated based upon a peak current analysis or an RMS current analysis. The effective capacitance for each net is compared against the maximum allowable capacitance to identify those nets that are at risk of failure due to the effects of electromigration.
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Balhiser David D.
Gentry Jason T
Harber Ronald G
Haskin Bryan
Marcoux Paul J.
Agilent Technologie,s Inc.
Bouscaren June L.
Kik Phallaka
Smith Matthew
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