Process and system for developing dynamic circuit guidelines

Details Process and system for developing dynamic circuit guidelines Process and system for developing dynamic circuit guidelines

2002-10-29

2004-12-28

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06836871

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates, in general, to development of dynamic circuits, and, more specifically, to a system and method for developing circuit design guidelines for silicon on insulator (SOI) dynamic circuits.
BACKGROUND OF THE INVENTION
The increasing speed of electronics in today's technology drives the need for faster and faster circuits. The increase in speed corresponds to a general effort to decrease size as well. High-speed circuits may be implemented in several different transistor technologies. Because of its size and speed characteristics, bulk complementary metal-oxide-semiconductor (CMOS) has been widely used to develop and design high-speed circuits. However, static CMOS circuits (i.e., a configuration of high-speed CMOS circuits using combinations of CMOS inverters) are limited by the number of components that are typically required. Static CMOS is also limited based on the number of p-type MOS (PMOS) transistors required in the circuits. Because hole mobility is significantly slower than electron mobility, PMOS devices are typically much larger than n-type MOS (NMOS) devices in order to transport an equivalent amount of current. The larger size not only increases the amount of space taken up by the PMOS, but also generally increases the parasitic capacitance over the entire system.
Dynamic circuits were developed to overcome some of these deficiencies in static CMOS circuits.
FIG. 1
is a circuit schematic illustrating a typical dynamic circuit configured as an OR circuit with a DNG field effect transistor (FET). Dynamic circuit
10
comprises an arrangement of FETs configured for a particular logic function having a two-phase cycle: precharge phase and evaluation phase. Dynamic circuit
10
is configured as an OR gate through parallel FETs
105
. Dynamic circuit
10
includes storage node
100
, which determines the signal on output node
101
through inverter
102
. Dynamic circuit
10
also includes DNG FET
103
with interstitial/DNG node
104
. DNG is ground (GND) spelled backwards. The DNG FET, also referred to as a clock FET or foot FET, is typically an n-channel device at the bottom of the pull-down tree whose gate is connected to a precharge clock (not shown), preventing a stack with static inputs from pulling down during the precharge phase. During the pre-charge phase, storage node
100
is effectively charged or pulled-up to V
DD
and isolated from ground, which, in turn, discharges or pulls output node
101
to ground. During the evaluation phase, storage node
100
may or may not be pulled-down to ground depending on the operation of the circuit, while output node
101
may or may not go to V
DD
. The output is communicated through inverter
102
coupled at the forward portion of dynamic circuit
10
.
Using a dynamic circuit configuration reduces the total number of PMOS transistors necessary, which generally reduces the required surface area as well as the resulting capacitance. The switching time is also decreased because of the pre-charging of the output node during the pre-charge phase. However, at today's speeds, even dynamic CMOS technology is beginning to reach speed limitations.
SOI technology has been used in place of bulk CMOS to achieve even faster switching speeds in both static and dynamic circuits. Because the junctions in SOI transistors are isolated from the substrate, the parasitic capacitance is substantially reduced, thus, reducing both the switching speeds and power consumption. However, even though SOI technology offers the benefits of faster switching at lower power consumption, the nature of the SOI's floating body (i.e., the substrate-isolated junctions) creates substantial problems in any circuit design, and especially in dynamic circuits.
The body voltage on SOI transistors may range (i.e., “float”), both dynamically and statically, anywhere from 0 volts to V
DD
. Unlike bulk CMOS technology, in which the body voltage is tied to the substrate and, therefore, does not vary, SOI body voltages may vary depending a many different criteria. As a result, each SOI-based dynamic circuit is usually modeled individually. This modeling process can be extremely time consuming and, therefore, expensive to implement. For complex circuits, many hundreds of man-hours of engineer time may be expended. Furthermore, current methods for designing such SOI dynamic circuits typically implement the use of “rules of thumb,” which are basic circuit design guidelines that are generalized enough to be used with a broad range of circuit types in many different noise level environments. However, because the “rules of thumb” are designed for broad applicability, it is difficult to use these circuit design aids to design a circuit to the most favorable conditions for speed. Therefore, even though the use of SOI transistors in dynamic circuits yields substantial speed and power benefits, the design process is extremely complex, requiring substantial ad hoc design and simulation.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a system and method for generating dynamic circuit design guidelines comprising modeling a dynamic circuit using one of a plurality of modeling circuit types, simulating the modeled dynamic circuit, extracting selected information from raw data measured during the simulating step, and analyzing the selected information to create the dynamic circuit design guidelines.


REFERENCES:
patent: 5452225 (1995-09-01), Hammer
patent: 5535370 (1996-07-01), Raman et al.
patent: 5768160 (1998-06-01), Kakegawa
patent: 5995425 (1999-11-01), Henkels et al.
patent: 6009256 (1999-12-01), Tseng et al.
patent: 6028983 (2000-02-01), Jaber
patent: 6072947 (2000-06-01), Roychowdhury et al.
patent: 6111422 (2000-08-01), Storino et al.
patent: 6163173 (2000-12-01), Storino et al.
patent: 6182258 (2001-01-01), Hollander
patent: 6189133 (2001-02-01), Durham et al.
patent: 6288572 (2001-09-01), Nowka
patent: 6300819 (2001-10-01), De et al.
patent: 6326814 (2001-12-01), Stasiak et al.
patent: 6378112 (2002-04-01), Martin et al.
patent: 6396305 (2002-05-01), Carlson
patent: 6567773 (2003-05-01), Rahmat et al.
patent: 6668358 (2003-12-01), Friend et al.
patent: 2003/0192014 (2003-10-01), Chng
patent: 2004/0002846 (2004-01-01), Lutz et al.
patent: 0529800 (1993-03-01), None
Assaderaghi et al., “Partially Depleted Silicon-on-Insulator (SOI): a Device Design/Modeling and Circuit Perspective,” IEEE, Nov. 2, 2000, pp. 201-204.*
Irwin et al., “Dynamic Circuit Synthesis Using the Owens Tool Set,” IEEE, Sep. 1998, pp. 205-210.*
Su et al., “Measurement and Modeling of Self-Heating in SOI NMOSFET's,” IEEE, Jan. 1994, pp. 69-75.*
Fayed et al., “Noise-Tolerant Design and Analysis for a Low-Voltage Dynamic Full Adder Cell,” IEEE, 2002, pp. 579-582.*
MacDonald et a., “Testing Dominno Circuits in SOI Technology,” IEEE, Dec. 2000, pp. 441-446.*
Foreign Search Report, Application No. GB 0325030.5, Examiner P. Marshall, date of search Feb. 9, 2004, pp. 1.
U.S patent application Ser. No. 10/282,342, Gunderson et al., filed Oct. 29, 2002.

Affiliated with

Also associated with

Rating

Process and system for developing dynamic circuit guidelines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process and system for developing dynamic circuit guidelines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process and system for developing dynamic circuit guidelines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3310126