Process and structure for semiconductor package

Details Process and structure for semiconductor package Process and structure for semiconductor package

2006-02-28

2006-02-28

Blum, David S. (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

C438S126000

Reexamination Certificate

active

07005327

ABSTRACT:
A packaging process for a semiconductor chip that includes the following steps. A carrier having an upper surface and a corresponding lower surface is provided. A photoresist layer is formed on the upper surface of the carrier. A plurality of photoresist openings that expose the carrier is formed in the photoresist layer. A plurality of openings that connects with the photoresist openings are formed in the carrier. A tape is attached to the lower surface of the carrier. The body is filled into the openings of the carrier. A chip is mounted onto the upper surface of the carrier and electrically connected therewith. Finally, the tape is removed from the lower surface of the carrier.

REFERENCES:
patent: 5200362 (1993-04-01), Lin et al.
patent: 5509203 (1996-04-01), Yamashita
patent: 5817545 (1998-10-01), Wang et al.
patent: 6022761 (2000-02-01), Grupen-Shemansky et al.
patent: 2002/0142520 (2002-10-01), Ino
patent: 2003/0022477 (2003-01-01), Hsieh et al.

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