Process and structure for measuring the planarity degree of a di

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

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257536, 257758, 324691, 324693, 324706, 324719, H01L 2358

Patent

active

055436331

ABSTRACT:
A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.

REFERENCES:
patent: 3974443 (1976-08-01), Thomas
patent: 4918377 (1990-04-01), Buehler et al.
patent: 5231051 (1993-07-01), Baldi et al.
Smith, Ralph J., Circuits, Devices and Systems, John Wiley & Sons, 1966 and 1971, p. 670.
Gniewek, J. and G. Lukianof, "Evaluating Insulation Layer Quality and Measuring Defect Density," IBM Technical Disclosure Bulletin 14(5):1433, New York, Oct. 1971.
Leinen, R. F., "Overview of Photomask Substrate Flatness Measurement Techniques," Solid-State Technology 21(5):77-81, Washington, May 1978.

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