Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-05-12
2002-04-23
Mai, Son L. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000
Reexamination Certificate
active
06376374
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor material. Devices which may be formed within the semiconductor material include MOS transistors, bipolar transistors, diodes and diffused resistors. Devices which may be formed within the dielectric include thin-film resistors and capacitors. Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer. The devices utilized in each dice are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric.
Delays in propagation of electrical signals between devices on a single dice limit the performance of integrated circuits. More particularly, these delays limit the speed at which an integrated circuit may process these electrical signals. Larger propagation delays reduce the speed at which the integrated circuit may process the electrical signals, while smaller propagation delays increase this speed. Accordingly, integrated circuit manufacturers seek ways in which to reduce the propagation delays.
For each interconnect path, signal propagation delay may be characterized by a time delay &tgr;. See E. H. Stevens,
Interconnect Technology,
QMC, Inc., July 1993. An approximate expression for the time delay, &tgr;, as it relates to the transmission of a signal between transistors on an integrated circuit is given by the equation:
&tgr;=
RC[
1+(
V
SAT/
/RI
SAT
)]
In this equation, R and C are, respectively, an equivalent resistance and capacitance for the interconnect path, and I
SAT
and V
SAT
are, respectively, the saturation (maximum) current and the drain-to-source potential at the onset of current saturation for the transistor that applies a signal to the interconnect path. The path resistance is proportional to the resistivity, &rgr;, of the conductor material. The path capacitance is proportional to the relative dielectric permittivity, K
e
, of the dielectric material. A small value of &tgr; requires that the interconnect line carry a current density sufficiently large to make the ratio V
SAT/
/RI
SAT
small. It follows, therefore, that a low-&rgr; conductor which can carry a high current density and a low-K
e
dielectric should be utilized in the manufacture of high-performance integrated circuits.
To meet the foregoing criterion, copper interconnect lines within a low-K
e
dielectric will likely replace aluminum-alloy lines within a silicon oxide dielectric as the most preferred interconnect structure. See “Copper Goes Mainstream: Low-k to Follow”,
Semiconductor International,
November 1997, pp. 67-70. Resistivities of copper films are in the range of 1.7 to 2.0 &mgr;&OHgr;cm. while resistivities of aluminum-alloy films are higher in the range of 3.0 to 3.5 &mgr;&OHgr;cm.
Despite the advantageous properties of copper, several problems must be addressed for copper interconnects to become viable in large-scale manufacturing processes.
Diffusion of copper is one such problem. Under the influence of an electric field, and at only moderately elevated temperatures, copper moves rapidly through silicon oxide. It is believed that copper also moves rapidly through low-K
e
dielectrics. Such copper diffusion causes failure of devices formed within the silicon.
Another problem is the propensity of copper to oxidize rapidly when immersed in aqueous solutions or when exposed to an oxygen-containing atmosphere. Oxidized surfaces of the copper are rendered non-conductive and thereby limit the current carrying capability of a given conductor path when compared to a similarly dimensioned non-oxidized copper path.
In view of the foregoing problems, the present inventor has recognized that copper metallization layers need an effective barrier material to prevent copper diffusion and an effective protective layer over the copper metallization to prevent oxidation of the copper. Existing processes for manufacturing such metallization layers are inefficient and are not economically viable for use in large-scale manufacturing operations.
BRIEF SUMMARY OF THE INVENTION
A process for providing one or more protected copper elements on a surface of a workpiece is set forth. In accordance with the process, a barrier layer is applied to the workpiece. If the barrier layer is not suitable as a seed layer for subsequent electroplating processes, a separate seed layer is applied over the surface of the barrier layer. One or more copper elements are then electroplated on selected portions of the seed layer or, if suitable, the barrier layer. If used, the seed layer is then substantially removed. At least a portion of a surface of the barrier layer is rendered unplatable while leaving the copper elements suitable for electroplating. A protective layer is then electroplated onto surfaces of the one or more copper elements.
A tool architecture for implementing the foregoing process is also set forth. The disclosed tool architecture may be used to minimize the number of wafer movements between the tool sets required to form a complete metallization layer structure.
The present invention provides a process and corresponding processing tool architecture that facilitates the implementation of efficient and economically viable large-scale manufacturing processes for use in making workpieces, wherein each workpiece has protected copper conductive elements disposed exterior to a barrier layer of the workpiece. The process and tool architecture, although applicable to a wide range of workpiece applications (semiconductor workpiece applications as well as non-semiconductor workpiece applications), are particularly suitable for use in the manufacture of one or more metallization levels of a semiconductor integrated circuit. In the particular embodiment of the process and tool architecture disclosed herein, the resulting protected metallization structure may be readily manufactured using a minimal number of processing tool sets and a minimal number of workpiece movements between the tool sets.
REFERENCES:
patent: 5827604 (1998-10-01), Uno et al.
patent: 5913144 (1999-06-01), Nguyen et al.
Berm Renee R.
Mai Son L.
Polit & Associates, LLC
Semitool Inc.
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