Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1986-09-25
1989-05-16
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Data refresh
365203, 365190, G11C 700
Patent
active
048315940
ABSTRACT:
The device refreshes the cells of an array of dynamic memory cells a row at a time during precharging of the bit or column lines. Normal access to read or write to the cells also refreshes them. Refresh circuits connect to the row line between the row address decoder and the cells, and include shift register stages connected to the row lines. A bit of one sense shifting through the stages indicates the row to be refreshed and a refresh signal connected to the stages times the refresh during the precharge. Using multiple, sequential refresh signals refreshes alternating rows of the cells.
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NEC Electronics Inc., Jan. 1985, ".mu.PD41264 262, 144-Bit Dual Port Dynamic NMOS RAM".
Chang Ki S.
Khosrovi Aman
Lou Perry W.
Bachand Richard
Bassuk Lawrence J.
Garcia Alfonso
Hecker Stuart N.
Sharp Melvin
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