Process and device for generating a clock signal

Details Process and device for generating a clock signal Process and device for generating a clock signal

1999-09-21

2002-10-15

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S362000, C375S371000, C375S375000, C375S373000, C327S156000, C327S162000, C331S00100A, C331S025000

Reexamination Certificate

active

06466635

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the field of electronics, and, more particularly, to a clock circuit.
BACKGROUND OF THE INVENTION
In digital data transmission systems, the clock signal for recovering the data within the receiver must be locked onto the clock signal used for transmission. Generally, the transmitter requires a very stable clock signal. To generate the clock recovery signal within the receiver, subsequently also referred to as the main clock signal, conventional clock recovery systems are used. The main clock signal may disappear temporarily for various reasons. In this case, provision is made to use a quartz crystal which generates a secondary clock signal having a frequency equal to the frequency of the main clock signal and, therefore, of the clock signal of the transmitter.
However, the frequency of the main clock signal and that of the secondary clock signal may differ by a few tens of parts per million (ppm) depending on the accuracy of the quartz crystal. As a result, on detecting the loss of the main clock signal and switching over to the secondary clock signal, digital data may be lost on account of the frequency and phase differences between the secondary clock signal and the main clock signal which has just been lost.
To remedy these drawbacks, one approach includes using a conventional phase-locked loop. One of the inputs of the phase comparator receives either the main clock signal if present, or the secondary clock signal generated by the quartz crystal should the main signal be lost. If the phase difference between the main signal, which has just been lost, and the signal transmitted by the quartz crsytal is relatively large when switching the signal at the input of the phase comparator, then large variations in phase and frequency occur. This is due, in particular, to the variation in the current injected into the filter of the phase-locked loop.
The gap between the frequency of the output signal from the phase-locked loop and the frequency of the main clock signal may then be temporarily relatively high. This leads, for example, to an output clock signal having a relatively higher frequency than that of the main clock signal. Under these conditions, the buffer memories which are customarily used to store the data received may be filled more rapidly than anticipated causing losses of data on reception.
Attempts have been made to reduce the value of the resistance of the filter of the phase-locked loop, in particular, with respect to the frequency jumps during the transient phase. However, this leads to larger time constants and, consequently, to higher durations for phase locking and phase jitter. These higher values are incompatible with certain applications.
SUMMARY OF THE INVENTION
An object of the present invention is to generate an output clock signal whose frequency gap with respect to the frequency of the main clock signal remains permanently below a predetermined threshold. The predetermined threshold may be small, for example, 100 ppm in absolute value, particularly during a temporary loss of the main clock signal. Should the main clock signal be lost, the generated output clock signal eliminates large jumps in phase and frequency which are detrimental to the reception of digital data. The reception of digital data may be information transmitted by a satellite link, for example.
The present invention provides a process for generating an output clock signal from a main clock signal having a predetermined main frequency and from a secondary clock signal generated by a quartz crystal. A frequency synthesizer, which receives the secondary clock signal, is controlled by a two-state control logic signal. The synthesizer selectively generates a first or a second auxiliary clock signal as the output clock signal. This is dependent upon whether the control signal is in its first or second state. The first auxiliary signal has a first auxiliary frequency equal to the value of the main frequency plus a predetermined frequency gap (about +50 ppm, for example) greater than the frequency accuracy of the secondary clock signal.
The second auxiliary signal has a second auxiliary frequency equal to the value of the main frequency minus the predetermined frequency gap (about −50 ppm, for example). One of the two states of the control logic signal is then determined as a function of the phase difference between the auxiliary clock signal delivered by the frequency synthesizer and, the main clock signal which may possibly be altered. The output clock signal is generated at the output of the frequency synthesizer. The output clock signal has a gap in frequency with respect to the main frequency and remains permanently below a predetermined threshold (about ±100 ppm, for example). This predetermined threshold depends on the frequency gap and on the frequency accuracy of the generator for the secondary signal, which may be a quartz crystal. This is done even when the main signal is lost.
In other words, the generated output clock signal is permanently one of the two auxiliary clock signals preprogrammed into the frequency synthesizer. The selection of which depends on the phase difference between the output signal from the synthesizer and the main clock signal. The predetermined threshold is about ±100 ppm for the gap in frequency of the output clock signal with respect to the frequency of the main clock signal. This is equal to the sum of the frequency gap preprogrammed into the synthesizer, and the frequency gap is about 50 ppm. The accuracy of the quartz crystal is about 50 ppm.
According to one mode of implementation of the process, the control logic signal has its first state when the auxiliary signal delivered by the synthesizer, i.e., the output clock signal, exhibits a phase lag with respect to the main signal. The synthesizer is forced to output the first auxiliary signal whose frequency is slightly greater than that of the main signal. The control logic signal has its second state when the auxiliary signal delivered by the synthesizer has a phase lead with respect to the main signal. The synthesizer is forced to output the second auxiliary signal, i.e., the one having a slightly lower frequency than that of the main signal.
An electronic device for generating an output clock signal includes a main input for receiving a main clock signal having a predetermined main frequency, as well as a generator for generating a secondary clock signal. The electronic device also includes a frequency synthesizer receiving the secondary clock signal as well as a two-state control logic signal. The frequency synthesizer generates as the output clock signal one of the first and second auxiliary clock signals. This is dependent upon whether the control logic signal is in its first or second states.
The first auxiliary signal has a first auxiliary frequency equal to the value of the main frequency plus a predetermined frequency gap greater than the frequency accuracy of the secondary clock signal. The second auxiliary signal has a second auxiliary frequency equal to the value of the main frequency minus the predetermined frequency gap.
The device further includes a controller having a first control input linked to the main input, i.e., receiving the main clock signal that may possibly be altered, and a second control input linked to the output of the frequency synthesizer, i.e., receiving one of the two auxiliary signals which is actually the output clock signal. The controller delivers the control logic signal with one of the these two states as a function of the phase difference between the respective signals present at the two control inputs.
According to one embodiment of the device, the controller provides the control logic signal with its first state when the signal present at the second control input, i.e., the output signal from the synthesizer, exhibits a phase lag with respect to the signal present at the first control input. The control logic signal is provided with its second state when the signal present at the second

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