Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-19
2006-09-19
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07111267
ABSTRACT:
An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.
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Galatenko Alexei V.
Gasanov Elyar E.
Lyalin Iliya V.
Zolotykh Andrej A.
Dinh Paul
LSI Logic Corporation
To Tuyen
Westman Champlin & Kelly P.A.
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