Error detection/correction and fault detection/recovery – Pulse or data error handling – Error detection for synchronization control
Reexamination Certificate
1997-09-19
2001-02-27
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error detection for synchronization control
C714S775000, C375S357000
Reexamination Certificate
active
06195783
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for synchronizing the block counter in an RDS radio data receiver and a circuit for carrying out the process.
BACKGROUND INFORMATION
U.S. Pat. No. 3,550,082 discloses a process for synchronizing a receiver with digitally transmitted code words formed using a non-binary, cyclic, error-correcting code. An offset word is additively superimposed on the code words to be transmitted, with a symbol of the alphabet being assigned to each symbol of the code word. In the receiver, the offset word is subtracted from the transmission signal and an error sample is generated by the generator polynomial underlying the code from the code word thus obtained, using polynomial division; the error sample is characteristic for the amount of deviation of the receiver's synchronization. Using a comparison of the error sample with all possible error samples, the exact amount of the synchronization deviation can be determined and thus the synchronization of the receiver can be restored.
The radio data system (RDS) is defined in DIN EN 50 067.
According to that reference, the information intended for the receiver is transmitted in groups. The individual groups are analyzed in different manners by the receiver. Each group consists of four blocks. One code word is transmitted in each block. Each code word consists of 26 bits, the first 16 bits of which are assigned to the information word and the following 10 bits are assigned to the check word. An additional offset word, also transmitted within the block and recognized as such in the receiver, is superimposed on each check word during transmission.
Depending on the group definition, either the same offset word (E) is superimposed on each block in the group or three offset words (A, B, D) used within a group form a cycle of four offset words with an additional variable offset word (C, C′). The cyclic use of offset words allows the transmitter to mark and the receiver to recognize the start of a group; when one of the cyclically used offset words is recognized in the receiver, its position in the group is also recognized. If the status of the block counter in the receiver matches this position at this time, the group clock that can be picked up at the block counter output is generated in the receiver synchronously with the transmitter. This allows the transmitted information words to be supplied to the analyzer.
When a receiver is turned on, or in the case of a switch-over to another transmitter or a longer shutdown of the transmitter, this match must be established for the first time or re-established, i.e., the receiver must be synchronized with the current transmitter. In Attachment C to the aforementioned DIN Standard EN 50 067, an embodiment of the block and group synchronization is explained for information. In the conventional embodiment for synchronization, the bits picked up at the output of the RDS receiver are supplied sequentially at the bit frequency to a 26-bit shift register. The stored bits are caused to cycle once in the shift register during each bit period and are received in a syndrome detection circuit, with an upstream register for polynomial division, for detection of the superimposed offset word. If the 26 bits stored in the shift register at a given time belong to the same block, a syndrome assigned to the offset word is detected in the circuit and a sync pulse can be picked up at the syndrome detection circuit output assigned to the recognized syndrome. This sync pulse is then analyzed in a control circuit, which, among other things, comprises a flywheel circuit.
SUMMARY OF THE INVENTION
The invention differs from this conventional process by the features depicted in FIG.
1
and summarized below.
The present invention provides a new method for synchronizing the receiver with the transmitter, taking advantage of the fact that a data processor allows a considerably higher data processing speed than that used in the conventional process.
In contrast to the related art, according to the present invention the stored 26 bits are sequentially X-OR gated once in a bit period with the bits of each of the defined offset words generated by an offset word generator in the data processor. This offset word generator is controlled by a counter whose status for the individual offset words corresponds to the normal assignment. At least six cycles of the stored bits are required for gating in each bit period according to the current definition. After each gating, the respective syndrome is computed; it becomes zero when the cycling 26 bits belong to the same block and when the offset word assigned to this block is used for the X-OR gating. When the syndrome becomes zero, the data processor in the radio data receiver is in sync with the transmitter-side data processor. To synchronize the remaining processes in the data processor, the block counter is set to the status assigned to the offset word used in the counter of the offset word generator when offset words are used cyclically, and the bit counter is reset to zero.
An advantage of the process according to the present invention is obtained by setting the block counter, for example, to the status of the two lowest positions of an address counter that controls the sequence for generating the offset words in the offset word generator.
An additional advantage or the process according to the present invention is obtained by employing, for example, a flywheel circuit to count the number of detections of the zero syndrome.
An additional advantage of the process according to the present invention is obtained by, for example, incrementing the number of detections in the flywheel circuit by one if, when the sync pulse occurs, correct or correctable data are stored in the shift register, and decrementing the number by one if the sync pulse occurs outside a block clock pulse or with an incorrect offset word.
The above and other advantages are obtained with a circuit according to the present invention, which, for example, offers a simple design of a control unit and a flywheel circuit and a simple design for the implementation of the syndrome detection circuit.
REFERENCES:
patent: 3550082 (1970-12-01), Tong
patent: 4945533 (1990-07-01), Schroeder et al.
patent: 4984249 (1991-01-01), Long et al.
patent: 5084891 (1992-01-01), Ariyavisitakul et al.
patent: 5111463 (1992-05-01), Zook
patent: 5157669 (1992-10-01), Yu et al.
patent: 5173925 (1992-12-01), Mizoguchi
patent: 5225839 (1993-07-01), Okurowski et al.
patent: 5325372 (1994-06-01), Ish-Shalom
patent: 5392289 (1995-02-01), Varian
patent: 5396653 (1995-03-01), Kivari et al.
patent: 5430740 (1995-07-01), Kivari et al.
patent: 5452333 (1995-09-01), Guo et al.
patent: 5473615 (1995-12-01), Boyer et al.
patent: 5539751 (1996-07-01), Sabel
patent: 5546464 (1996-08-01), Raith et al.
patent: 5636208 (1997-06-01), Chang et al.
patent: 5745503 (1998-04-01), Kuusinen
patent: 5784390 (1998-07-01), Masiewicz et al.
Din En 50 067—Spezifikation des Radio-DatenSystems (RDS), 1992.
Hegeler Wilhelm
Nyenhuis Detlev
Blaupunkt-Werke GmbH
Cady Albert De
Kenyon & Kenyon
Lamarre Guy J.
LandOfFree
Process and apparatus for synchronizing the block counter in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process and apparatus for synchronizing the block counter in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process and apparatus for synchronizing the block counter in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2581925