Process and apparatus for placing cells in an IC floorplan

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

10830542

ABSTRACT:
Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. The coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.

REFERENCES:
patent: 5225991 (1993-07-01), Dougherty
patent: 5535134 (1996-07-01), Cohn et al.
patent: 5661663 (1997-08-01), Scepanovic et al.
patent: 5682321 (1997-10-01), Ding et al.
patent: 5712793 (1998-01-01), Scepanovic et al.
patent: 5838583 (1998-11-01), Varadarajan et al.
patent: 5867398 (1999-02-01), Scepanovic et al.
patent: 5870312 (1999-02-01), Scepanovic et al.
patent: 5892688 (1999-04-01), Scepanovic et al.
patent: 5971588 (1999-10-01), Scepanovic et al.
patent: 6249902 (2001-06-01), Igusa et al.
patent: 6282693 (2001-08-01), Naylor et al.
patent: 6292929 (2001-09-01), Scepanovic et al.
patent: 6415425 (2002-07-01), Chaudhary et al.
patent: 6480991 (2002-11-01), Cho et al.
patent: 6536028 (2003-03-01), Katsioulas et al.
patent: 6567967 (2003-05-01), Greidinger et al.
patent: 6748574 (2004-06-01), Sasagawa et al.
patent: 7036102 (2006-04-01), Andreev et al.
U.S. Appl. No. 10/688,460, filed Oct. 17, 2003, Process and Apparatus for Fast Assignment of Objects to a Rectangle (22 pages).
U.S. Appl. No. 10/694,208, filed Oct. 27, 2003, Process and Apparatus for Placement of Cells in an IC During Floorplan Creation (26 pages).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process and apparatus for placing cells in an IC floorplan does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process and apparatus for placing cells in an IC floorplan, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process and apparatus for placing cells in an IC floorplan will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3792027

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.