Process and apparatus for memory mapping

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

10830739

ABSTRACT:
A plurality of user-defined memories are mapped to pre-defined basic memories, such as defined on a base platform. The user-defined memories are dividing into classes of similar memories. A mapping technique is selected for members of a selected class of user-defined memories that minimizes the ratio (maxi,j(USEDi,j/AVAILi,j)) of basic memories that have been mapped to basic memories that are available for mapping. If the number of different memory mappings is smaller than a threshold the mapping technique is applied to each user-defined memory. If the number of different memory mappings is greater than the threshold, the groups are arranged in ordered queues of single memory types based on a mapping price and the mapping technique is selected based on a memory of each group and is applied to each user-defined memory in the respective group.

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