Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2000-03-20
2003-02-18
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S015000, C710S016000, C710S022000
Reexamination Certificate
active
06523071
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates to the configuration of the direct memory access transfer mode of motherboards or host computers, and more particularly to a process of configuring a motherboard receiving attachment to device(s), such as peripheral storage, in accordance with the particular cable being employed for the attachment of the device(s) to the motherboard.
BACKGROUND ART
The AT Attachment (ATA) storage interface has become very popular on most personal computers. It provides attachment between a host and storage systems for systems manufacturers, software suppliers and system integrators. The storage systems may be for instance disk drives or CDROM drives or any device or storage peripheral being placed on the interface.
FIGS. 1A
to
1
C illustrate the interface cabling diagram of a host computer, or more simply a motherboard
3
, with one or two devices which are connected in a daisy chain configuration.
FIG. 1A
illustrates the attachment of two devices, a device
1
which is configured in a master mode, and a device
2
which operates as a slave. The attachment is achieved by means of AT Attachment cable
4
, for instance the popular 40-connector attachment cable, also known under the designation Integrated Drive Electronics or IDE.
FIGS. 1B and 1C
show more particularly the attachment of one unique device to the Motherboard by means of IDE cable
4
which, in this case, operates as a master device.
The AT Attachment interface has been subject a strong effort of standardization in order to increase speed, to improve interchangeability and to bring additional functions. Most of the recommendations and regulations which have been developed in this particular technical area can be found in the publications of the Technical Committee T13 for the National Committee on Information Technology Standards (NCITS), which is accredited and operates under the rules approved by the American National Standards Institute (A.N.S.I.)
Recent developments brought to the AT Attachment interface have been formulated in the ATA-3/ATA-4 specification which define the connectors and cables for physical interconnection between the host and the devices, as well as the electrical/logical characteristics of the interconnecting signals, the commands and protocols involved in the operation of the storage device. These developments particularly recommend the replacement of the traditional 40-conductor cable by a 80-conductor cable—known as an Ultra-ATRA 66 cable—in order to improve signal quality for data transfer modes that do not require a 80-conductor cable assembly. In the near future, the popular 40-conductor IDE cable is thus expected to be superseded by the Ultra-ATA 66 cable.
Ultra-ATA cable has 80 conductors with every two conductors having one conductor being connected to the ground in order to improve the quality of the signal which is conveyed via the cable. Because of the improvement brought to the quality of the signal, the 80-conductor cable is capable of conveying higher speeds without data corruption. Ultra-ATA cable is required for Ultra-DMA modes which are greater than mode 2 (33 Megabytes per second) and is recommended for Ultra-DMA. The commands and protocols which are involved in this Ultra-ATA 66 cable are specified in the ATA-4 standards as well as in the T13 document “d98133, New timing for Ultra DMA”
A motherboard which supports the Ultra-ATA/66 is capable of operating at different modes and speeds, the Ultra-ATA/66 mode but also the lower modes. Since both 40-conductor cables and 80-conductor cables share the same physical connector, it is highly desirable to give the possibility to the processor located on the motherboard to determine which physical cable is being present for the attachment of the peripheral storage(s). Indeed, should the motherboard be configured to operate at 66 megabytes per second via a traditional IDE cable, it is most likely that data corruption might occur. Therefore ATA4 specification recommends that a cable detection circuit be implemented in order to reliably determine the presence of the 80-conductor cable for the attachment of storage devices to the motherboard, before allowing higher speeds and higher modes. Document 1153D “
AT Attachment with Packet Interface Extension
(ATA/ATAPI-4)”, published as ANSI NCITS 317-1998 and available from ANSI, 11 West 42
nd
Street, New York, N.Y. 10036, as well as document “
Proposal for Ultra ATA/
66”, referenced T13/D98133, revision 1 of the T13 Committee, address this particular problem of 80-conductor cable detection.
The method which is proposed in these prior art documents is based on the use of a particular pin of the AT attachment interface, pin-
34
which is also used for the Passed_on_diagnostics (PDIAG#) signal. Normally, the PDIAG# signal is involved in the communication between the master device
1
and the slave device
2
after the execution of the diagnostic tests in the latter. More specifically, as soon as the slave device has passed its diagnostic tests after power-on reset, the latter is expected to issue an electrical low level on the PDIAG# pin in order to inform the master device of the correct execution and completion of the diagnostic procedure. Any device which complies with ATA-3 or subsequent standards is expected, then, to release the PDIAG# pin no later than after the first command following a power on or hardware reset sequence.
In the Standards ATA-4, the cable detection is based on a special arrangement which is brought to the 80-conductor cable in order to achieve the cable detection. Indeed, in the 80-conductor cable, the pin-
34
, which normally carries the PDIAG# signal in the usual 40-conductor cable, is isolated between the host connector and the devices connectors. Therefore, the PDIAG# signal can no longer be transmitted to the pin-
34
on the host side. On the host side the pin
34
(PGIAG#) is grounded in the enclosure of the connector and a pull-up resistance is provided on this pin on the motherboard.
The prior art method of ATA-4 specifications involves, during the Power-On Self Tests (POST), a determination of the electrical status of the pin
34
on the motherboard, which is performed after the release by the devices of the pin-
34
which, as evoked above, is normally expected no later than after the first command received by the device. An alternative method is also known to take advantage of pin-
34
in the cable detection process. This involves the use of a capacitor which is connected between the ground and the host connector. The device enters into a detecting step where it tries to detect the charging of the capacity which, of course, can not be detected if a 80-cable is present since pin-
34
of the motherboard is isolated from Pin-
34
of the devices. Such alternative is particularly addressed in document “
Proposal for Ultra ATA/
66”, referenced T13/D98133, revision 1 of the T13 Committee
The methods which are summarized above remain effective as long as the slave device shows a behavior which is that being expected, that is to say it releases the PDIAG# pin after the first command received during the first IDE transaction with the board. However, should the device behave slightly differently—which is the case for many CDROM devices—and not strictly conform to the ATA-3 specifications, the result might be a corruption of data. Indeed, if, for one reason, a CDROM slave device, for instance, does not release the pin-
34
after the first command being received from the motherboard, then the motherboard will find that pin-
34
carries a low level, which results from the incorrect behavior of the slave device, and not from the internal ground wiring of pin
34
of a potential 80-conductor cable being plugged in the connector. Therefore, in this case, the processor under control of the bios would make an incorrect interpretation of the low state of pin-
34
, and will see in the low state the evidence of the presence of a 80-conductor cable which is not present. In this situation, since the proces
Klinger Werner
Oudet Pascal
Gaffin Jeffrey
Hewlett--Packard Company
Kim Harold
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