Process and apparatus for adaptive bus termination

Details Process and apparatus for adaptive bus termination Process and apparatus for adaptive bus termination

1997-11-24

1999-07-06

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

326 30, G06F 1300

Patent

active

059192526

ABSTRACT:
Process and apparatus for reducing termination resistors on a CPU data bus and a CPU address bus. The reduced termination resistors are switched in, such as by a transistor switch or other switch, only during read operations when a CPU is receiving data from its bus or a CPU data bus only during hold acknowledge cycles. This increases the speed of the buses and allows the buses to be operation dependent. Further, power can be reduced during certain busing operations, resulting in cooler running and more reliable operations. Uses for adaptive termination includes microprocessor buses for data lines, address lines and control lines; peripheral devices for matching impedance to cable; and D/A converters. Variations on the device includes pull-up, pull-down, multiple levels/strengths, programmable with EPROM type cell, multiple units in the same package, and multiple values in the same package.

REFERENCES:
patent: 4220876 (1980-09-01), Ray
patent: 4748426 (1988-05-01), Stewart
patent: 5029284 (1991-07-01), Feldbaumer et al.
patent: 5309569 (1994-05-01), Warchol
patent: 5467455 (1995-11-01), Gay et al.

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