Probabilistic noise analysis

Details Probabilistic noise analysis Probabilistic noise analysis

2008-03-11

2010-02-09

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07661083

ABSTRACT:
A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

REFERENCES:
patent: 5568395 (1996-10-01), Huang
patent: 7093223 (2006-08-01), Becer et al.
patent: 7146588 (2006-12-01), Marathe et al.
S. Vrudhula, et al., Probabilistic Analysis of Interconnect Coupling Noise, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, No. 9, Sep. 2003, pp. 1188-1203.

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