Private cache miss and access management in a multiprocessor sys

Details Private cache miss and access management in a multiprocessor sys Private cache miss and access management in a multiprocessor sys

1996-12-18

1998-10-27

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711130, 711138, G06F 1208

Patent

active

058290290

ABSTRACT:
A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a "siphon" operation to service the request of the other CPU.

REFERENCES:
patent: 5398325 (1995-03-01), Chang et al.
patent: 5434993 (1995-07-01), Liencres et al.
patent: 5581732 (1996-12-01), Dann
patent: 5659707 (1997-08-01), Wang et al.
patent: 5708792 (1992-04-01), Hayes et al.

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