Priority transaction support on the PCI-X bus

Details Priority transaction support on the PCI-X bus Priority transaction support on the PCI-X bus

2001-09-30

2004-10-05

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S107000, C710S306000, C710S313000, C370S402000

Reexamination Certificate

active

06801970

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to scheduling transactions on computer bus systems, and in particular, support for priority transaction scheduling on computer bus systems employing the high-performance extension (PCI-X) to the peripheral component interconnect (PCI) protocol.
2. Description of the Related Art
PCI and PCI-X are bus systems widely used in computers. PCI-X provides performance improvements over PCI because PCI-X operates at higher clock frequencies made possible by a register-to-register protocol and other protocol enhancements, such as an attribute phase and split transactions. PCI-X also is supposed to lead to follow-on technologies that include better performance capabilities. This is important because with current PCI-X, if the rate of servicing a device on the bus requiring immediate servicing were to drop below a threshold, the computer system would crash. The device, for example, could be the computer system's main microprocessor. One possible improvement could be to enhance stability from computer system crashes and enhance the servicing of transactions for such devices to benefit performance.
Current PCI capable devices have a Scheduler to implement transaction Ordering Rules to determine which transaction in a queue will be handled next. The Ordering Rules are rules for emptying the queues. They are specified to guarantee a consistent view of data by all devices in the system and rational behavior between multiple devices and their software drivers (if any). Conventional PCI Ordering Rules apply globally to all transactions without regard to the underlying communications semantics. The Relaxed Ordering attribute in PCI-X transactions allows certain ordering requirements to be indicated explicitly on a transaction-by-transaction basis, providing a tool to help system designers and software writers achieve better overall performance. The current PCI capable devices, however, have no way of determining the relative priority between transactions communicated to them from other devices. The current PCI-X protocol and scheduling is still subject to system crashes because a clear priority usage model is not provided for devices that should have priority for exclusive or early handling.
There are three types of queues that the Scheduler controls. These queues are the Posted Write, Completion, and Request queues, each of which handles a different transaction class. Certain classes of transactions are permitted to bypass other classes for handling next, and other transactions are not so permitted. For example, the PCI-X Relaxed Ordering attribute may be used to allow a memory write transaction to pass other memory writes and to allow a Split Read Completion to pass memory writes.
Therefore, for these and other reasons it is imperative to improve transaction handling priority without adding cost to the system. A better transaction handling scheme may predicate the longevity of PCI-X.
SUMMARY OF THE INVENTION
Embodiments of the present invention feature support for controlling transaction priority for PCI-X. These embodiments provide indicia of priority to communicate to PCI-X-to-PCI-X bridges that a transaction tagged by the indicia should be scheduled, using a special handling instruction, ahead of any other transaction not invoking this special handling instruction. The special handling instruction allows the priority transaction to be scheduled first. The indicia of priority can be implemented by setting an unused bit(s) in a PCI-X attribute field or multiplexed with another used signal bit(s) to schedule the associated transaction as the priority transaction over the other transactions that do not have their corresponding bit set. The present invention is useful for interrupt messaging, audio streams, video streams, isochronous transactions or for high performance, low bandwidth control structures used for communication in a multiprocessor architecture across PCI-X.
Embodiments of the present invention feature a technique, in a computer system, of providing indicia of priority for PCI-X transactions. According to the technique, a plurality of PCI-X phases is created in the computer system. A transaction priority mechanism for PCI-X is provided in the computer system by inserting priority indicia into an unused attribute portion (e.g., at the location of an unused bit(s)) of the plurality of PCI-X phases.


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“HARTIK 3.0: a portable system for developing real-time applications” by Lamastra, G.; Lipari, G.; Buttazzo, G.; Casile, A.: Conticelli, F. (abstract only).*
“A flexible compatible PCI interface for nuclear experiments” by Saleh, H.; Engels, R.; Reinartz, R.; Reiinhart, P; Rongen, F. (abstract only).

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