Priority resolver and “near match” detection...

Details Priority resolver and “near match” detection... Priority resolver and “near match” detection...

2005-12-13

2005-12-13

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S049130

Reexamination Certificate

active

06976123

ABSTRACT:
An apparatus and method is disclosed for a CAM priority match detection circuit which determines a “near match” condition using a current-based decoder. The decoder uses n input lines and m complement lines to generate 2noutputs, where the 2n outputs form a priority code for a given CAM word. The priority match detection circuit determines which CAM word or words out of a plurality of CAM words has the least amount of mismatching bits and prioritizes the CAM word or words in accordance with such determination.

REFERENCES:
patent: 5053991 (1991-10-01), Burrows
patent: 6510509 (2003-01-01), Chopra et al.
patent: 6591317 (2003-07-01), Schzukin et al.
patent: 2003/0115426 (2003-06-01), Rosenbluth et al.

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