Television – Receiver circuitry
Patent
1997-04-21
2000-06-06
Flynn, Nathan
Television
Receiver circuitry
348 10, 709219, H04N 700
Patent
active
060725435
ABSTRACT:
A priority order processing circuit is disclosed for an MPEG system adapted to determine the priority order of events generated from a multiprocessor of a decoding system utilizing MPEG1 and MPEG2 schemes while controlling operations of the system. The priority order processing circuit includes a video buffer verifier writing controller for generating a writing request signal when a situation exists for storing data in an external memory, a video buffer verifier reading controller for generating a reading request signal when a situation exists for reading the stored data, a display controller for generating a display request signal in response to recovered data received therein, a motion compensation reading controller for generating a motion compensation reading request signal when motion compensation for the stored data is requested, a motion compensation writing controller for generating a motion compensation writing request signal when the motion compensation is requested, and a priority order controller for determining a priority order for various request signals generated, respectively, from the video buffer verifier writing controller, video buffer verifier reading controller, display controller, motion compensation reading controller and motion compensation writing controller while generating a service code for executing a data processing service.
REFERENCES:
patent: 4633392 (1986-12-01), Vincent et al.
patent: 4796176 (1989-01-01), D'Amico
patent: 4803617 (1989-02-01), Berarducci
Flynn Nathan
Samsung Electronics Co,. Ltd.
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