Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2005-05-03
2005-05-03
Vo, Tim (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S107000
Reexamination Certificate
active
06889276
ABSTRACT:
A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions. This is accomplished by splitting an allocated shared bus time into frames of equal length. When a bus request is received the technique determines whether the bus request in a current frame is for an asynchronous transaction or an isochronous transaction. If an asynchronous transaction bus request exists it is processed, otherwise an isochronous transaction bus request is processed. Bus requests for an isochronous transaction are queued if received while an asynchronous transaction is currently being processed. Asynchronous transactions are given priority until a current frame time has ended. In one embodiment, at the start of a new frame (which becomes the current frame) any queued isochronous transactions are processed before asynchronous transactions of the current frame are given priority. In another embodiment, queued isochronous transactions are only processed at the start of a new frame if they are from two frames prior to the new frame.
REFERENCES:
patent: 5544324 (1996-08-01), Edem et al.
patent: 5778218 (1998-07-01), Gulick
Universal Serial Bus Specification, Compaq, Digital Equipment Corporation, IBM PC Company, Intel, Microsoft, NEC, Northern Telecom; Revision 1.0, pp. 1 and 2, and pp. 54 through 83, (Jan. 15, 1996).
Standards Project P1394 IEEE Draft Standard for a High Performance Serial Bus, IEEE Standards Committee, 2 cover pages, pp. i-ii, (Jul. 7, 1995).
Hewlett--Packard Development Company, L.P.
Vo Tim
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