Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-02-29
2004-03-02
Vo, Tim (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S107000
Reexamination Certificate
active
06701399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to scheduling of asynchronous and isochronous transactions on a shared bus, and more particularly to giving priority to asynchronous transactions to the extent that isochronous transaction latency does not exceed a desired time.
2. Description of the Related Art
Many computer systems utilize a shared bus that carries multiple types of traffic. For example, some shared buses carry both asynchronous and isochronous traffic. A Peripheral Component Interconnect (PCI) bus is an example of a shared bus that has been used to carry both asynchronous and isochronous traffic. While asynchronous traffic can be delayed indefinitely without adversely affecting real-time data streams, computer system performance can be adversely affected when the asynchronous traffic is delayed. Further, since isochronous traffic is time dependent, it requires a certain bandwidth and worst case latency. A multimedia stream (video and audio signal) is an example of isochronous traffic. Multimedia streams utilize an isochronous transport mechanism to ensure that data is delivered at least as fast as it needs to be displayed. Further, isochronous transport mechanisms have been utilized to ensure an audio signal is synchronized with a video signal. Provided bandwidth and latency requirements for isochronous traffic are met, latency of the isochronous traffic has not had an adverse effect on real-time performance.
A number of techniques have been employed to ensure that isochronous traffic had access to a shared bus for a given amount of time within a given frame. These methods have included static allocation of bandwidth and timer/counter based mechanisms which attempted to detect when isochronous transactions were complete. These prior methods have normally guaranteed isochronous latency at the expense of asynchronous latency. That is to say, the isochronous bus requests were fulfilled without consideration of the asynchronous bus requests. As a general rule, this resulted in increased latency for the asynchronous requests. In addition, trying to predict isochronous transaction requirements based on time averages has normally complicated system design.
SUMMARY OF THE PRESENT INVENTION
A system according to the present invention implements a technique for scheduling asynchronous and isochronous transactions on a shared bus that reduces asynchronous latency while keeping isochronous latency below an acceptable level. This is accomplished by splitting an allocated shared bus time into frames of equal length. When a bus request is received the technique determines whether the bus request in a current frame is for an asynchronous transaction or an isochronous transaction. If an asynchronous bus request exists it is processed, otherwise an isochronous bus request is processed. Bus requests for an isochronous transaction are queued if received while an asynchronous transaction is currently being processed. Asynchronous transactions are given priority until a current frame time has ended.
In one embodiment, at the start of a new frame any queued isochronous transaction requests are processed before asynchronous transaction requests of the current frame are given priority. In another embodiment, queued isochronous transaction requests are only processed at the start of the new frame if they are from two frames prior to the new frame. An advantage of the present technique is that it can be implemented using a few latches and a few relatively simple logic gates. Another advantage of the present technique is that scheduling of isochronous transactions are based on isochronous source requests.
REFERENCES:
patent: 5202999 (1993-04-01), Lenthall et al.
patent: 5544324 (1996-08-01), Edem et al.
patent: 5778218 (1998-07-01), Gulick
patent: 5862360 (1999-01-01), Meaney et al.
patent: 6032211 (2000-02-01), Hewitt
patent: 6397277 (2002-05-01), Kato et al.
patent: 6415367 (2002-07-01), Baxter et al.
Standards Project P1394 IEEE Draft Standard for a High Performance Serial Bus, IEEE Standards Committee, 2 cover pages, pp. i-ii, 207-242, (Jul. 7, 1995).
Universal Serial Bus Specification, Compaq, Digital Equipment Corporation, IBM PC Company, Intel, Microsoft, NEC, Northern Telecom; Revision 1.0, Jan. 15, 1996, pp. 1 and 2, and pp. 54 through 83.
Compaq Information Technologies Group
Vo Tim
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