Priority encoding for FIFO memory devices that interface...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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Reexamination Certificate

active

06266748

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to First-In-First-Out (FIFO) memory devices, and more particularly to FIFO memory devices that interface multiple ports to a data receiving device.
BACKGROUND IF THE INVENTION
First-In-First-Out (FIFO) memory devices are widely used to store data. FIFO memory devices generally include one or more FIFO memory blocks. In a FIFO memory block, data generally is stored in a sequential order as data is written into the memory block. The FIFO memory block typically is sequentially read in the same order as it was written. Thus, the data that is first written into the FIFO device is also the data that is first read from the FIFO device.
FIFO memory devices are widely used to buffer data in network applications. In network applications, data packets may be stored in the FIFO memory device in the sequential order that they are written. For routing or distribution, the data is sequentially read starting from the first data that was written.
A plurality of FIFO memory blocks may be used in a FIFO memory device that interfaces a plurality of ports to a data receiving device. For example, an integrated circuit 4-Port Multliplexer-FIFO is marketed by Integrated Device Technology, Inc., the assignee of the present application, as Device IDT77305. See the Data Sheet entitled “UtopiaFIFO™ 4-Port (128×9×4) Multiplexer-FIFO”, IDT77305, January 1996. The IDT77305 is a high-speed, low power 4:1 multiplexed FIFO with multiple programmable modes of operation. Within the IDT77305, the input FIFOs act as intermediate queues for the input streams, to allow synchronization with a common output stream. A round robin sequencer sequentially selects one of four FIFOs to output data.
As described above, FIFO memory devices may be used to interface a plurality of ports to a data receiving device. One important application of FIFO memory devices is under a specification known as the Universal Test and Operation Physical (PHY) Interface for Asynchronous Transfer Mode (ATM) specification or the UTOPIA specification. The UTOPIA specification defines an interface between a plurality of ports and an ATM device. In this application, the FIFO memory device synchronizes input and output of data between relatively slow physical devices and a relatively high speed ATM device.
UTOPIA is a Physical Layer to ATM Layer interface that was standardized by the ATM Forum. It has separate transmit and receive channels and specific handshaking protocols. UTOPIA Level 2 includes dedicated address signals for both the transmit and receive directions that allow the ATM Layer device to specify which of the four physical (PHY) channels it is communicating with. In contrast, UTOPIA Level 1 does not use address signals. Instead, key handshaking signals are duplicated so that each channel has its own signals.
In UTOPIA Level 1 operation, it may be desirable to efficiently select which of the four channels, also referred to as ports, communicates with the ATM device. Since UTOPIA Level 1 does not use addressing, the ATM device can enable communications from multiple ports. Since it is possible for more than one port to contain data, it may be desirable to allow only one of the enabled ports to be selected at any time. The selection should preferably allow efficient communications between the relatively low speed ports and the relatively high speed data receiving device.
As described above, it is known to provide a round robin sequencer in order to allow multiple ports to sequentially communicate with the data receiving device. See also, U.S. patent application Ser. No. 08/664,873, filed Jun. 17, 1996 to Chan et al., entitled “First-In-First-Out Memory Device With Programmable Cell Sizes and Multiplexing Functions”, assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference. Notwithstanding the use of round robin sequencers to allow multiple ports to communicate data to a data receiving device, there continues to be a need to efficiently interface a plurality of ports to a data receiving device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved interfacing from a plurality of ports to a data receiving device.
It is another object of the present invention to provide interfacing from a plurality of ports to a data receiving device that can allow relatively low speed ports to efficiently communicate data to a relatively high speed data receiving device.
These and other objects are provided, according to the present invention, by a priority encoding interface that transmits data to the receiving device from a highest priority FIFO memory block that is selected from at least two of a plurality of FIFO memory blocks until the highest priority FIFO memory block is empty. The interface inhibits transfer of data to the data receiving device from remaining ones of the FIFO memory blocks, even though they contain data, until the highest priority FIFO memory block is empty. Transmission of data from the highest priority FIFO memory block and inhibited transfer of data from remaining ones of the FIFO memory blocks, take place in response to an indication from the data receiving device that the data receiving device is enabled to receive data from the at least two of the FIFO memory blocks.
Accordingly, a plurality of FIFO memory blocks are provided, a respective one of which receives data from a respective one of a plurality of ports. The data receiving device can enable any or all of the ports to receive data therefrom. However, notwithstanding enablement of more than one port by the data receiving device, the present invention allows data transmission to the data receiving device from the highest priority port that is selected from the enabled ports until the FIFO from the highest priority port is empty, even though the other enabled ports contain data.
Once enabled and transfer begins, the highest priority FIFO memory block will continue to transmit data to the data receiving device, until the associated FIFO memory block is empty. Transfers from other memory blocks are disabled, notwithstanding that the other ports are also enabled and may include data in their FIFO memory blocks. Data transmission from the remaining FIFO ports also may be disabled, notwithstanding the data receiving device ceases to enable the highest priority port, until the enabled FIFO memory block is empty.
Accordingly, transfers from the relatively slow speed ports may be conducted efficiently by allowing the FIFO to be emptied rather than stopped in midstream. Once emptied, the next highest priority port can then transmit its full FIFO contents to the data receiving device. Efficient interfacing between a plurality of ports and a data receiving device may thereby be provided.
The present invention is preferably implemented as an integrated circuit that interfaces a plurality of ports, such as serial ports for a plurality of physical devices that are connected by twisted copper pairs or other transmission media to an ATM device, such as an ATM switch. The interface is preferably provided by logic devices on an integrated circuit chip. However, the interface may also be provided by a processor on the integrated circuit chip that executes programmed instructions.
In a preferred embodiment of the present invention, each of the FIFO memory blocks provides an indication that the FIFO block is empty. A priority encoder identifies the highest priority FIFO memory block from the at least two of the FIFO memory blocks that are enabled to receive data by the data receiving device, in response to an indication from the data receiving device that the data receiving device is enabled to receive data from at least two of the FIFO memory blocks. A logic circuit produces a FIFO selection signal for the identified highest priority FIFO memory block, in response to the priority encoder and to the indications that the FIFO blocks are empty. The FIFO selection signal remains active, until the identified highest priority FIFO block is

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