Priority encoding and decoding for memory architecture

Details Priority encoding and decoding for memory architecture Priority encoding and decoding for memory architecture

1997-08-28

1999-12-21

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Access arbitrating

Access prioritizing

710240, 710 41, 710 40, 711151, G06F 1318

Patent

active

060063033

ABSTRACT:
A shared resource access priority encoding/decoding and arbitration scheme takes into account varying device requirements, including latency, bandwidth and throughput. These requirements are stored and are dynamically updated based on changing access demand conditions.

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Barnaby et al., "Patent Disclosure: Priority Encoding and Decoding for Memory Architecture", Invention Date: Jan. 23, 1996; Document Date: Oct. 8, 1996; pp. 1-14.

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