Priority encoder for a content addressable memory system

Details Priority encoder for a content addressable memory system Priority encoder for a content addressable memory system

1997-05-30

1999-10-12

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

395435, 395478, G06F 1342, G06F 1200

Patent

active

059648570

ABSTRACT:
A priority encoder for generating a priority-encoded address which identifies the highest priority request line. According to one priority scheme, the active request line having the lowest address has the highest priority. The priority encoder is capable of generating the priority-encoded address by determining information corresponding to the most significant bits of the priority-encoded address and using this information in the computation of less significant bits of the priority-encoded address. Using purely combinatorial logic, including switch elements, the priority encoder is capable of computing lower order bits using feedback signals resulting from the computation of higher order bits, allowing successive computation of priority-encoded address bits, without necessitating the use of clocks or delay elements.

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Mano, M. Morris, "Digital Design", Second Edition, Prentice Hall, pp. 170-173, 1984.

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