Priority encoder circuit and method

Details Priority encoder circuit and method Priority encoder circuit and method

2006-05-09

2006-05-09

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S220000, C365S049130

Reexamination Certificate

active

07043601

ABSTRACT:
A system and method for high speed generation of a global address corresponding to the highest priority active matchline sense output signal received after a CAM search-and-compare operation is disclosed. A priority encoder having blocks of multiple match resolver circuits arranged in a logical order of priority receives a plurality of active matchline sense output signals. Each block of multiple match resolver circuits generates a flag signal and a local address corresponding to the highest priority active matchline sense output signal received. Control logic receives flag signals from the multiple match resolver circuits, and identifies the highest priority multiple match resolver circuit that has received an active matchline sense output signal. The control logic then disables all lower priority multiple match resolver circuits such that only the local address generated by the highest priority multiple match resolver circuit is passed by the priority encoder. The flag signals are also decoded to provide a logical address of the highest priority multiple match resolver circuit. The passed local address and the logical address of the highest priority multiple match resolver circuit are concatenated to provide the global address of the highest priority active matchline sense output signal received by the priority encoder.

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