Priority encoder and encoding method

Details Priority encoder and encoding method Priority encoder and encoding method

2000-10-23

2002-10-08

Jean Pierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S050000

Reexamination Certificate

active

06462694

ABSTRACT:

RELATED PATENT APPLICATION
This application claims priority from Japanese patent application number 11-302088, filed Oct. 25, 1999, which is hereby incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a priority encoder and an encoding method using the priority encoder, and more particularly to a compact and high-speed priority encoder and a high-speed encoding method.
2. Description of Related Art
The function of a priority encoder is to output a code corresponding to the highest-priority input line among a plurality of input lines having a true value when input signal is input to more than one of input lines which are prioritized and given codes.
FIG. 13
shows an example of a prior encoder and
FIG. 14
is a truth table showing inputs and outputs of the priority encoder shown in FIG.
13
. In the priority encoder
100
(all the inputs are negative logic) shown in
FIG. 13
, when more than one of eight data inputs (IN
7
N, IN
6
N, IN
5
N, IN
4
N, IN
3
N, IN
2
N, IN
1
N, and IN
0
N) are simultaneously activated (“0”), a 3-bit code (binary code) representing the input having the highest priority among the activated inputs (this input will be hereinafter referred to as “highest-priority input”) is output. As shown in
FIG. 13
, this code is generated by combining input signals and their inverted signals.
The input IN
7
N has the highest priority. The smaller the number t in INtN is, the lower the priority is. In this example, the highest-priority input is determined with respect to an active input (“0”). As shown in
FIG. 14
, when the input IN
7
N having the highest priority has the highest-priority true input, the output signals (“A2 A1 A0”) of the encoder
100
are “0 0 0”, and when the input IN
0
N having the lowest priority has the highest-priority true input, the output signals are “1 1 1”. Thus, the output signals are signals in which a binary code corresponding to the number t of INtN is inverted. The mark “−” in
FIG. 14
denotes “don't care”. An output GS is a signal representing the presence or absence of active input signals into the encoder
100
. An input EI and an output EO are signals for expansion, and the output EO is connected to the input EI of the next-stage encoder.
FIG.
15
(
a
) shows another example of a priority encoder and FIG.
15
(
b
) is a truth table showing inputs and outputs of the priority encoder shown in FIG.
15
(
a
). A priority encoder
110
shown in FIG.
15
(
a
) comprises a selector circuit
116
and a plurality of priority encoders
112
and
114
. FIG.
16
(
a
) shows an example of a 4-to-2 priority encoder
112
, and FIG.
16
(
b
) is a truth table showing inputs and outputs of the priority encoder
112
shown in FIG.
16
(
a
).
FIG. 17
shows an example of the selector circuit
116
. Unlike the priority encoder
100
shown in FIG.
13
and its inputs and outputs shown in
FIG. 14
, the input IN
0
N has the highest priority in the priority encoder
110
. The larger the number t in INtN is, the lower the priority is. As shown in FIG.
15
(
b
), when the input IN
0
N having the highest priority has the highest-priority true input, the output signals (“A2 A1 A0”) of the encoder
110
are “0 0 0”, and when the input IN
7
N having the lowest priority has the highest-priority true input, the output signals are “1 1 1”. Thus, the output signals are represented in binary notation, indicating the number t in INtN of the highest-priority input having a true value.
Eight data inputs (IN
0
N, IN
1
N, IN
2
N, IN
3
N, IN
4
N, IN
5
N, IN
6
N, and IN
7
N) are divided into two groups, namely a group of four higher-priority inputs (IN
0
N, IN
1
N, IN
2
N, and IN
3
N) and a group of four lower-priority inputs (IN
4
N, IN
5
N, IN
6
N, and IN
7
N). The 4-to-2 priority encoders
112
and
114
receives these two groups of inputs, respectively. The encoders
112
and
114
each output a 2-bit binary code representing the active highest-priority input of the four inputs. The selector circuit
116
outputs lower-order 2 bits (“A1 A0”) of the output signals (“A2 A1 A0”) in response to the output from the higher encoder
112
.
By combination of a selector circuit and a plurality of priority encoders, and by expanding the input and output of the selector circuit, the priority encoder can be configured as a greater whole encoder, for example, a 64-to-6 priority encoder
120
, by using four 16-to-4 priority encoders
122
, as shown in FIG.
18
. However, since the priority encoder contains a number of components as shown in
FIG. 13
, a combination of a plurality of priority encoders as shown in
FIG. 18
increases the number of components in the greater whole encoder, which leads to the increase in the circuit size of the greater whole encoder, the increase in the number of circuit stages, and the reduction of processing speed.
SUMMARY OF THE INVENTION
Objects of the present invention are to downsize the priority encoder by reducing the number of components and to achieve a high-speed encoding.
The priority encoder of the present invention comprises:
higher-order-bit encoding means for outputting a higher-order m-bit code corresponding to the group having the highest priority among those groups out of 2
m
groups distinguished by higher-order m bits to which true values are input (hereinafter referred to as “highest-priority group distinguished by the higher-order m bits”); each of the 2
m
groups consisting of 2
n
input lines having common higher-order m bits of (m+n)-bit output code; and
lower-order-bit encoding means for outputting a lower-order n-bit code corresponding to the input line having the highest priority among input lines to which true values are input; the input lines being part of 2
n
input lines which make up the highest-priority group distinguished by the higher-order m bits and which are distinguished by the lower n bits of the (m+n)-bit output code.
An encoding method using the priority encoder of the present invention comprises the steps of:
outputting higher-order bits corresponding to the group having the highest priority among those groups distinguished by higher-order bits to which true values are input (hereinafter referred to as “highest-priority group distinguished by the higher-order bits”); each of the groups distinguished by higher-order bits comprising input lines which are grouped on the basis of higher-order bits of the code; and
outputting lower-order bits corresponding to the input line having the highest priority among input lines to which true values are input; the input lines being part of input lines which make up the highest-priority group distinguished by the higher-order bits and are distinguished by the lower bits of the output code.


REFERENCES:
patent: 4346369 (1982-08-01), Macy
patent: 5519881 (1996-05-01), Yoshida et al.
patent: 5555397 (1996-09-01), Sasama et al.
patent: 5602545 (1997-02-01), Ishii et al.
patent: 5714949 (1998-02-01), Watabe
patent: 5964857 (1999-10-01), Srinivasan et al.

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