Priority determining apparatus using the least significant bit a

Details Priority determining apparatus using the least significant bit a Priority determining apparatus using the least significant bit a

1999-12-30

2000-12-26

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Signals

36518905, 365194, 711151, 711158, G11C 700

Patent

active

061669709

ABSTRACT:
Disclosed is a DDR SDRAM device capable of inputting and outputting a plurality of data within one period of a clock; and, more particularly, a priority determining apparatus for determining data output priority between even and odd data. The DDR SDRAM device according to the present invention includes a priority signal generator for receiving a least significant bit of a column address signal and a first control signal which is activated when read or write operation is carried out and for generating a priority signal to determine an order of output of the even and odd data stored in each of the pipeline latch circuits.

REFERENCES:
patent: 5809278 (1998-09-01), Watanabe et al.
patent: 5809539 (1998-09-01), Sakakibara et al.
patent: 6079001 (2000-06-01), Le et al.

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