Priority cross-bar decoder

Details Priority cross-bar decoder Priority cross-bar decoder

2005-01-04

2005-01-04

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S100000, C710S316000, C710S037000, C370S388000

Reexamination Certificate

active

06839795

ABSTRACT:
A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the cross-bar decoder (70) to either activate or deactivate routing of the triplet signals (84, 86,88) through the cross-bar decoder (70). The routing cells (72-82) are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells (72, 74, 76) and are extracted at the column routing cells (76, 80, 82). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder (70) until all high priority I/O pins are used. The outputs of the cross-bar decoder (70) are coupled to respective I/O pins (170, 172, 174) by way of respective driver circuits (212, 216, 236).

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