Priority-based shared bus request signal mediating circuit

Details Priority-based shared bus request signal mediating circuit Priority-based shared bus request signal mediating circuit

1998-07-14

2001-07-31

Etienne, Ario (Department: 2155)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S240000, C710S241000

Reexamination Certificate

active

06269418

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a bus request signal mediating circuit and, more particularly, to a bus request signal mediating circuit for mediating between a plurality of bus accessing circuits sharing a single bus line.
(b) Description of the Related Art
When a single bus is shared among a plurality of bus accessing circuit, a bus request signal mediating circuit is generally used for mediating the use of the single bus by the plurality of accessing circuits. An example of such a bus request signal mediating circuit is described in JP-A-4(1992)-52749.
FIG. 1
shows the bus request signal mediating circuit described in the publication mentioned above. The bus request signal mediating circuit is provided for mediating between three accessing circuits
14
,
15
and
16
, and comprises a first register section
401
for latching bus request signals
101
,
102
and
103
, a selector
402
for selecting one of the bus request signals from first register section
401
based on a control signal
407
specifying the address of first register section
401
, a RAM
403
for storing the priority data between the bus request signals in memory cells which are accessed by the address specified by an output from selector
402
, and a second register section
404
for latching outputs from RAM
403
to deliver a bus use authorization signal to one of the bus accessing circuits
14
,
15
and
16
.
When any number of accessing circuits
14
,
15
and
16
output bus request signals
101
,
102
and/or
103
, the bus request signals are latched by first register section
401
and input to RAM
403
through selector
402
as an address signal for RAM
403
. RAM
403
delivers an authorization signal
104
,
105
or
106
to one of accessing circuits
14
,
15
and
16
through register
404
based on the bus request signals and the priority stored in RAM
403
among the bus request signals
101
,
102
and
103
.
An OR gate
406
suppresses an output from first register section
401
while second register section
404
delivers the authorization signal, thereby suppressing further inputs from other accessing circuits. After the specified accessing circuit finishes the processing using bus line
12
, OR gate
405
delivers an end signal to reset register
404
, which enables further mediating operation between the bus request signals
101
,
102
and
103
. The priority data stored in RAM
403
can be updated by a new priority data
409
, which is supplied from outside the mediating circuit by using a control signal
408
to switch the input of selector
402
to an address signal
407
.
The bus request signal mediating circuit as described above has a problem in that if the highest priority accessing circuit outputs the accessing signal in succession, the bus line cannot be used by other lower priority accessing circuits, resulting in monopoly of the single bus by the highest priority accessing circuit.
In addition, if the number of accessing circuits increases due to a complicated circuit configuration, update of the priority data consumes a large amount of time due to a large number of bits to be stored in the RAM.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a bus request signal mediating circuit which is capable of preventing the monopoly of a bus line by a higher priority accessing circuit and capable of updating the priority data with a reduced time length.
The present invention provides a bus request signal mediating circuit comprising a latch section for latching a plurality of bus request signals from respective bus accessing circuits, a priority data storage section for storing priority data specifying priority among the plurality of bus request signals, a mediating section for mediating the plurality of bus request signals based on the priority data, an authorization section for allowing the bus accessing circuits to use a bus line in an order of a result of mediation by the mediating section, and a bus request signal suppressing section for preventing the latch section from receiving a new bus request signal occurring after a predetermined time interval and prior to a completion of all pending bus request signals received within the predetermined time interval, the predetermined time interval being defined as the time which begins with receipt of a first one of the plurality of bus request signals and ends after a predetermined delay.
In accordance with the bus request signal mediating circuit of the present invention, when a plurality of accessing circuits deliver bus request signals at the same time, the bus request signal mediating circuit suppresses a further bus request signal from any of the accessing circuits until the accesses by the then existing bus request signals are completed. The suppression applies to all of the accessing circuits, and thus a new bus request signal is inhibited until the lowest priority bus request signal is processed successive to the processing for the higher priority bus request signal.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.


REFERENCES:
patent: 5025370 (1991-06-01), Koegel et al.
patent: 55-041039 (1980-03-01), None
patent: 63-116260 (1988-05-01), None
patent: 1189750 (1989-07-01), None
patent: 31268 (1991-01-01), None
patent: 3-002949 (1991-01-01), None
patent: 338760 (1991-02-01), None
patent: 4-42342 A (1992-02-01), None
patent: 4-52749 (1992-02-01), None
patent: 5151153 (1993-06-01), None
patent: 5-143526 (1993-06-01), None
patent: 11-031123 (1999-02-01), None
Japanese Office Action dated Feb. 15, 2000.
English translation of portions of Feb. 15, 2000 Japanese Office Action.

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