Priority-based memory prefetcher

Details Priority-based memory prefetcher Priority-based memory prefetcher

2007-11-01

2010-11-30

Thai, Tuan V (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07844780

ABSTRACT:
A method for preforming memory prefetching and scheduling prefetch commands inside the memory controller is disclosed. A set of prefetch commands is generated based on a stream of Read requests intended for a system memory, and the prefetch commands are stored in a low priority queue (LPQ). A set of regular commands is generated based on a stream of Read and Write requests intended for the system memory, and the regular commands are stored in a centralized arbiter queue. One of the prefetch commands is issued from the LPQ depending on the status of the other queues in the memory controller.

REFERENCES:
patent: 2005/0091460 (2005-04-01), Rotithor et al.
patent: 2006/0064532 (2006-03-01), Hur
patent: 2007/0005934 (2007-01-01), Rotithor et al.
Memory Prefetching Using Adaptive Stream Detection, Ibrahim HUr, Calvin Lin, Dec. 2006, Procedding of the 39th Annual IEEE/ACM International Symposium on Microarchitecture.
Ibrahim Hur, Calvin Lin, adaptive history based memory schedulers, Proceddings of the 37th International Symposium on Microarchitecture, Micro-37'04, 2004.

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