Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-07-19
2001-10-30
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S240000
Reexamination Certificate
active
06311244
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to bus priority allocation in a digital system and more particularly to a method of allocating access in a bus arrangement among a plurality of discrete and/or integrated modules and an associated apparatus.
Many schemes have been implemented for purposes of providing prioritized access to bus arrangements in digital systems. One of skill in the art will readily recognize that the concept of priority in a digital system is crucial since certain components or modules such as, for example, a CPU require low latency accesses to the bus arrangement. At the same time, however, other groups of components or modules may require access to the bus arrangement in a way which provides for reasonably low latency access and for fairness among the groups, particularly in instances where the various components or modules which make up these groups are in substantially continuous contention for the use of the bus arrangement. It is submitted that bus contention between module/component groups has become a significant problem in view of the recent and continuing movement toward streaming type processing environments since bus arrangements experience higher utilization levels, as will be further discussed at an appropriate point below.
In prior art systems, groups of modules or components which require substantially equal bus access are pre-assigned the same (hereinafter multi-assigned) priority level. Thereafter, during the operation of such a system, some sort of mechanism is employed each time a multi-assigned priority level is to receive a bus grant so as to delegate the grant to one of that level's multi-assigned modules in an attempt to ensure fair bus access. For example, a random number generator may be utilized in determining which module actually receives the bus grant. Unfortunately, the aforedescribed scheme adds considerable complexity through the need for the mechanism which is required to select one module from a group of multi-assigned modules which are on a particular priority level.
Another concern with regard to past priority allocation implementations relates to flexibility. Specifically, typical priority allocation implementations do not provide for adjusting relative priorities of components/modules during the operation of the system. That is, once an initial priority configuration has been established at system startup, that startup configuration is maintained for the duration of system operation. This inflexibility may be disadvantageous in a variety of different circumstances as the operation of a system progresses. For example, processing may move from a first task using one group of modules to a second task using another group of modules. If system priorities do not adjust accordingly, the overall throughput of the system may suffer.
As mentioned briefly above, still another concern resides in the problem of bus contention with regard to the way in which priority allocation implementations of the past operate in a streaming environment. Specifically, it should be appreciated that different modules interconnected by one bus arrangement may possess different data transfer capabilities. In many instances, these differences in transfer rate capabilities are handled by using a buffer to store data at a rate which is determined by a source module. Thereafter, the data is transferred to a destination module over the bus arrangement at a rate which is determined by the destination module. Buffering, however, is disadvantageous for several different reasons. As a first reason, relatively expensive local memory is required at one of the modules to perform the buffering task whereby to increase overall costs. As a second reason, this buffering approach is inherently inconsistent with an efficient streaming environment as is contemplated by the present invention.
As will be seen hereinafter, the present invention provides a highly advantageous priority allocation approach and associated apparatus which resolve the foregoing concerns and which provides still further advantages that have not been seen heretofore.
SUMMARY OF THE INVENTION
As will be described in more detail hereinafter, there is disclosed herein a method and associated arrangement for use in priority allocation in a bus interconnected digital multi-module system which may include discrete and/or integrated modules.
In one aspect of the invention, at least one bus interconnects a plurality of modules in a predetermined way. During the operation of the system, each of the modules is configured for requesting the use of the bus with each module being granted its request based on an established scheme of priorities. Each module is assigned to an initial priority and, during the operation of the system, at least one module is reassigned to a priority which is different than its initial priority.
In another aspect of the invention, it is established that a particular module, based on a request made by that module, has the highest priority for the use of the bus in relation to any other modules concurrently requesting the use of the bus. Nevertheless, the grant of the bus to that particular module is refused with the bus being granted to a different module based on predetermined parameters. In one embodiment, the predetermined parameters include priority allocation. In one feature, bus grants may be determined based, at least in part, on “speed values” assigned to the modules. The speed values are determined in view of relative data transfer capabilities (i.e., data rates) of the modules.
In still another aspect of the invention, a bus arrangement includes at least one bus which interconnects at least three modules in a predetermined way. Each of the modules is capable of requesting the use of the bus and each module is granted its request based on an established scheme of priorities. During operation of the system, a set of priorities is established for use as the scheme of priorities such that the number of priorities is equal to the number of modules in the system. Thereafter, one module is assigned to each priority such that subsequent grants of the bus are made based, at least in part, upon the priorities.
In one feature, one module which receives a grant, based on the priorities, and at least one other module are reassigned to different ones of the priorities.
In another feature, at least two priority groups are established for use in granting module requests such that each priority group includes a relative priority in relation to the other group or groups and each priority group includes a predetermined number of priority levels such that the total number of priority levels among all of the priority groups is equal to the total number of modules. When two or more modules within different priority groups simultaneously request the use of the bus, arbitration is performed among the requesting modules based, at least in part, on the relative priority levels of the priority groups to which the requesting modules belong so as to determine a winning priority group. Thereafter, the use of the bus is granted to the requesting module within the winning priority group.
In still another feature, at some point during the operation of the system, a new arrangement of priority groups is established which is different than an initially established priority group arrangement such that each new priority group includes a new relative priority in relation to the other new priority groups. The modules are then reassigned to the new priority groups such that when two or more modules within different new priority groups simultaneously request the use of the bus, arbitration among the requesting modules may be performed based, at least in part, on the new relative priorities of the new priority groups so as to determine a winning priority group. Thereafter, the bus is granted to the requesting module within the winning priority group.
REFERENCES:
patent: 4263649 (1981-04-01), Lapp, Jr.
patent: 4814974 (1989-03-01), Narayanan et al.
patent: 4847757 (1989-07-01), S
Lincoln Bradford Clark
Sheafor Stephen James
Wei James Yuan
Fusion Micromedia Corporation
Pritzkau Michael
Ray Gopal C.
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