Prioritized bus request scheduling mechanism for processing...

Details Prioritized bus request scheduling mechanism for processing... Prioritized bus request scheduling mechanism for processing...

2006-11-07

2006-11-07

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S151000, C710S309000, C710S310000

Reexamination Certificate

active

07133981

ABSTRACT:
A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.

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