Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-02-16
2002-09-10
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C029S830000
Reexamination Certificate
active
06448509
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to printed circuit boards (“PCBs”) in general, and in particular, to a PCB with an integral heat spreader for use in semiconductor packages and a method of making such a PCB.
2. Description of the Related Art
To be practically useful, semiconductor chips are typically housed in robust packages that protect them from the environment, permit them to be reliably interconnected with associated components, and enable them to effectively dissipate heat to the ambient.
The current trend toward electronic devices that are more compact, yet faster and more functional, has created a corresponding demand for semiconductor packages that are smaller, yet which permit a more dense mounting of components dissipating greater amounts of heat. One response to this demand has been the development of so-called ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) types of packages that substitute lands or balls of solder on the bottom of the package for conventional leads. Such packages surface mount with a “footprint” that is the same size as the package itself. To accommodate chips dissipating greater amounts of power, special “power” versions of these packages (e.g., “PBGA” packages) have been developed. These typically involve mounting the chip(s), directly or indirectly on a heat sink, or “slug,” that is laminated or soldered to the top or bottom side of an interconnection substrate, such as a PCB.
In a paper presented at the “'95 Flip Chip, BAG, TAB & AP Symposium,” entitled, “Conduction-Cooled Ball Grid Array,” (® 1995 Semiconductor Technology Center, Inc.), M. Hundt, et al. of SGS-Thomson Microelectronics, Inc., describe a BGA package in which a copper heat sink, or “slug,” is laminated to the bottom surface (i.e., the surface on which the solder balls mount) of a PCB having a central rectangular opening in it. A chip is epoxied to the slug in the opening and is wire-bonded to the surrounding PCB substrate to effect electrical interconnection of the chip. The bottom surface of the heat slug is soldered to a multilayer main board having a relatively thick ground plane. Plated-through via holes in the main board conduct heat from the bottom of the heat slug to the ground plane to convey heat away from the chip. The authors claim that this design reduces the internal thermal resistance (&THgr;
jc
) of the package to a value that is typically less than 1 degree C/Watt for most sizes of chip.
While the foregoing type of package provides one solution to the problem of packaging chips dissipating larger amounts of heat in smaller packages, its benefits are somewhat offset in a cost-competitive environment by the additional costs associated with the fabrication and assembly of the special PCB and separate heat sink. A long-felt need therefore exists in the industry for a PCB having an enhanced heat dissipating capability for use in a power version of a BGA-, LGA- and LCC-type of semiconductor package.
BRIEF SUMMARY OF THE INVENTION
This invention provides a method of making a low-cost PCB having an integral heat spreader for use in a PBGA-, PLGA- or PLCC-type of semiconductor package that uses only conventional PCB fabrication methods and materials.
The method includes forming one or more clearance openings through a first layer of a metal at selected locations therein corresponding to the desired locations in the PCB of “clearance vias,” i.e., locations where it is desired to conduct an electrical signal from the upper surface of the PCB to its lower surface. A lay-up is then formed in which the first layer of metal becomes the central layer of a “sandwich” respectively comprising a lower layer of a metal, a lower layer of a dielectric material, the first, or central layer of metal, an upper layer of a dielectric material, and an upper layer of a metal.
In one embodiment of the PCB, the dielectric layers comprise a composite of a fibrous dielectric material impregnated with a partially cured thermosetting resin. The lay-up is simultaneously pressed and heated between the platen of a heated press. The pressure forces some of the soft resin from the dielectric layers into the clearance openings in the central layer of metal, and some of the resin to the surfaces of the dielectric layers, where the resin wets the opposing surfaces of the respective metal layers. The heat cures the resin, simultaneously forming a resin insulator within each of the clearance openings and adhering the layers of the lay-up together in an integral laminate.
A plurality of apertures is formed through the laminate, and the interior walls of each aperture is plated with a metal to form a “via” in the laminate, i.e., a continuous metal path through the aperture between the upper and lower layers of metal. The “clearance vias” are created by forming selected ones of the apertures at the locations of the clearance openings, such that the central layer of metal is isolated from the metal paths through the apertures by the insulators in the clearance openings.
The remaining apertures are formed at locations other than those of the clearance openings, such that the central layer of metal is integrally connected to the metal paths through the selected apertures. These apertures correspond to “thermal vias,” i.e., locations in the PCB, such as immediately below a semiconductor chip, where it is desirable to conduct heat from the upper layer of metal to the central layer, which acts as a “heat spreader” to spread the heat throughout the length and breadth of the PCB, and thence to the lower layer of metal, where it can be conducted away into, e.g., a heat-sinking “main board” to which the package is mounted.
A better understanding of the above and other features and advantages of the present invention may be obtained from a consideration of the detailed description below of the exemplary embodiments thereof, particularly if such consideration is made in conjunction with the associated drawings.
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patent: 0692823 (1996-01-01), None
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Hundt, Mike, et al., “Conduction-Cooled Ball Grid Array”, '95 Flip Chip, BGA, TAB & AP Symposium, pp. 101-106.
Amkor Technology Inc.
Cuneo Kamand
Lawrence Don
Norris Jeremy
Parsons James E.
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