Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-26
2004-03-09
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S004000, C703S014000
Reexamination Certificate
active
06704919
ABSTRACT:
RELATED APPLICATION DATA
This application claims priority to Japanese Patent Application JP 2000-196790, and the disclosure of that application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a printed circuit board wiring structure checkup system, and in particular, it relates to a printed circuit board wiring structure checkup system including a layout method (design method) of a bulk capacitor which is to be disposed in the periphery of a high speed IC.
2. Related Art
Generally, a bulk capacitor for use as a circuit element on a printed circuit board in a recent electronic device is used for supplying a constant dc power and current to the device when all signal pins therein are switched at the same time under a maximum capacity load.
It is also known that it functions at the same time to supply a charge to a decoupling capacitor which is used in conjunction with the bulk capacitor.
A value of capacitance of the above-mentioned bulk capacitor is known to need to have an appropriate capacitance value capable of supplying a dc power (current) over a predetermined value when all the signal pins are switched at the same time, and also capable of supplying an adequate charge to all decoupling capacitors to be served by the bulk capacitor.
Further, it is also known that in order to be able to supply an adequate charge quickly to a power dropout portion or the decoupling capacitor, a position of the bulk capacitor must be in the vicinity of an IC and the decoupling capacitor which are the objects to supply the charge.
However, it is seldom that actual values of capacitance and actual positions of bulk capacitors now in use are specified precisely in a strict sense. For example, as to the capacitance, in most cases, it is designated by manufacturers who supply ICs or circuits regarding a preferred positioning, the number to be disposed and a capacitance value of the bulk capacitors, or they are determined on the basis of a result of testing by actually positioning bulk capacitors on a test board.
Also, it is often practiced that the position of the bulk capacitor, the number of arrangement thereof and circuit constants thereof are imported from the past experiences of operation. Further, also as to the position of arrangement of the bulk capacitor, it is often defined ambiguously such as “position as near as possible to a target IC”.
By the way, in line with an increasingly high speed signal in ICs and an increasing number of pins, a quantity of current or a pass-through current flowing from a power supply to the ground, and/or a frequency thereof are increasing remarkably.
In addition, because of an increasing number of power supply pins or ground pins there is such a problem that it is difficult to know which bulk capacitor is effective to which pin, or which bulk capacitor is responsible for supplying a charge to which decoupling capacitor.
Further, because it is anticipated that a quantity of current flowing into a power plane and/or a frequency thereof will change with an increasing speed of its digital signals, there arises such a problem when actually determining its circuit constants, the number of its provision and the position of the bulk capacitors, that it is difficult quantitatively to determine how many bulk capacitors with how much capacitance are where to be positioned.
Still further, there was such a problem that a supply of electric charge to a corresponding decoupling capacitor from its host bulk capacitor was not sufficient thereby delaying an effective response of the decoupling capacitor so as to increase a radiation noise resulting from a bounce noise (a noise which occurs when a potential of a power source plane or a ground plane varies locally).
SUMMARY OF THE INVENTION
The present invention is contemplated to solve the above-mentioned problems associated with the conventional printed circuit board design and checkup system, and to provide a novel printed circuit board wiring structure checkup system which is capable of verifying if a capacitance value of a bulk capacitor corresponding to power pins, ground pins and decoupling capacitors in an object circuit is adequate, and/or if its position in the circuit is optimal.
The novel printed circuit board wiring structure checkup system in accordance with one embodiment of the invention contemplated to solve the above-mentioned problems associated with the prior art is directed to a printed circuit board wiring structure checkup system capable of checking if a tentative wiring structure temporarily designed on a printed circuit board is acceptable or not. The check up system is comprised of: an object extract unit for extracting part numbers of all ICs from a list of parts listing all parts existing on its wiring and sorted into groups, extracting a characteristic specification of each of the ICs, and selecting a high speed IC as an object of checkup on the basis of “a rise time” or “a fall time” of a peripheral pulse current of each IC which is contained in the characteristic specification; a sorting unit for sorting all part numbers of all parts connected to a power line of the wiring structure including the high speed IC selected into groups of power pins, bulk capacitors and decoupling capacitors, for each of high speed ICs extracted above; an optimum capacitance value computing unit for computing an optimum capacitance value the bulk capacitor should have; a plurality of comparison units for comparing, for example, a capacitance value of a tentative design value given to the bulk capacitor and the optimum capacitance value computed; a first countermeasure display unit for displaying a first countermeasure instruction when a difference larger than a predetermined value is found between items of comparison in any one of the plurality of comparison units; an optimum positioning compute unit for computing an optimum position to dispose the bulk capacitor; and a second countermeasure display unit for displaying a second countermeasure instruction when a difference larger than a predetermined value is found in comparison of the tentative design position of the bulk capacitor with the optimum position thereof computed above.
Namely, there are provided such advantages according to one embodiment of the present invention that an optimum position to place the bulk capacitor, which is an object of checkup, on a printed circuit board and an optimum capacitance value thereof are calculated using simple mathematical expressions, that it is verified whether or not the design value of the bulk capacitor is in the vicinity of the optimum value computed and/or whether or not the bulk capacitor is placed in the vicinity of the optimum position computed, and that if the actual position and actual capacitance value of the bulk capacitor differ largely from the optimum position and optimum value calculated above, an appropriate message is displayed instructing to change the position and the capacitance value of the bulk capacitor to become optimal. Thereby, according to the invention, it is enabled to define a corresponding relation of each bulk capacitor with a respective power pin (or ground pin) and a respective decoupling capacitor for which the bulk capacitor is responsible in a grand integrated circuit including grand networks of several hundreds thereof and power supplies, and also to determine the optimum capacitance value and the optimum position for these bulk capacitors without the needs of replacing the conventional design procedures and increasing the design cost.
Still further, there is another advantage such that the bounce noise which is considered to arise in the periphery of the power pin described above can be suppressed substantially.
In accordance with another embodiment of present invention, there is provided an apparatus for checking a wiring structure designed for a printed circuit board. The apparatus may comprise: an object extract unit for selecting a high speed IC to be checked; a sorting unit
Araki Kenji
Yokoyama Ayao
Depke Robert J.
Holland & Knight LLP
Levin Naum B
Siek Vuthe
LandOfFree
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