Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-30
2001-07-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06256769
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to printed circuit board routing techniques. More particularly, the invention relates to apparatus and methods for defining circuit routing paths between electronic components on a substrate by varying the effect of minimum length routing rules.
BACKGROUND OF THE INVENTION
Routing is a process used to define certain paths between various electronic components on a substrate such as a printed circuit board (PCB). The routing process results in a routing pattern that, when etched onto a printed circuit board as a pattern of traces, provides the required electrical connectivity between the components. Typically, during PCB fabrication, copper traces or other copper features are developed on copper foils by chemical etching and plating processes. The copper foils are then laminated to dielectric materials to form the PCB.
PCB complexity ranges from simple, one-layer boards to high density, multilayer boards. A multilayer board can be a dense, 3-dimensional maze of copper traces and copper plated holes. For these boards, powerful computers and sophisticated routing software must be used to be able to accomplish a routing task. Companies that specialize in developing routing software, or “routing engines,” continue to enhance existing routing algorithms to handle higher density PCB designs. Occasionally, however, board designers that use existing routing software have to develop new routing techniques to achieve a desired result using an existing routing engine.
Automatic routing techniques are commonly used to define a routing pattern for a system of electronic components on a substrate. The routing pattern, which comprises a plurality of routing paths that have been defined between pins of various components, is used to establish the electrical connections between the various components on the substrate. Typically, a goal of an automatic routing technique is to determine the most efficient routing pattern for the system, given certain constraints or “routing rules.”
In timing critical circuit designs, board routing must comply with strict routing rules such as minimum length, maximum length, and matched length rules to ensure proper timing of a corresponding electronic circuit. Thus, if the length of a routing path defined between two electronic components is shorter than required, the routing path must be lengthened to comply with the applicable routing rules. An automatic routing engine usually adds this extra length in the form of a serpentine pattern.
Well known software packages are widely used to define routing patterns during the PCB design process. These routing engines, however, can be inadequate for routing near areas on the PCB where the routing density is high. An application specific integrated circuit (ASIC), for example, typically communicates with numerous electrical components the PCB and, consequently, requires a large number of traces.
The minimum required path length between two electrical components is determined based on, among other things, the signal delay required between the components. Typically, when the so-called “Manhattan” route (ie., where the path is routed along an x-y grid) does not provide sufficient delay, a “serpentine” pattern is added in the path. Existing routing engines have proven incapable of providing proper routing in regions of high routing density because the serpentine patterns quickly exhaust the available space on the PCB in the vicinity of the component before all of the paths can be defined. Consequently, the routing pattern cannot be defined.
Other high pin count electronic components, such as pin grid arrays (PGAs) and ball grid arrays (BGAs), also create high route density areas on PCBs since a significant number of traces must enter or exit the wiring area surrounding the high pin count device(s). Since there is a finite number of routing channels available through the area, multiple routing layers may be required to complete the routing path. Obviously, this increases board complexity and cost While routing channels are already at a premium in high density areas, serpentines may additionally reduce the available routing space by blocking the routing channels. This can make the board unroutable or may necessitate additional layers.
Thus, it would be advantageous to PCB designers engaged in the process of board routing to have an automatic routing technique that improves board routability, reduces the number of copper layers needed to route a board, and reduces the time necessary to complete the routing process, by eliminating the blockage of routing channels in high density wiring areas by serpentine traces.
SUMMARY OF THE INVENTION
The present invention satisfies these needs in the art by providing apparatus and methods for defining circuit routing paths between electronic components on a substrate. In a typical implementation, the invention can be embodied as a software product carried on a computer-readable medium, such as a magnetic or optical disk, memory device, or even a computer network (ie., the software product could be distributed over the Internet). Alternatively, the invention can be practiced by using conventional routing engine software in a new way, in accordance with the methods described below.
A method for defining routing paths between components on a substrate, such as a printed circuit board, includes associating one or more routing rules with connections between the components. At least one of the routing rules can be a minimum length routing rule. A first set of routing paths between the components is defined while ignoring the minimum length routing rule. Then, the first set of routing paths is modified by enforcing the minimum length routing rule.
Preferably, the modified set of routing paths is defined based on the first set of routing paths. Each routing path in the modified set of routing paths corresponds to a respective routing path in the first set of routing paths. At least one of the routing paths in the modified set of routing paths is longer than the corresponding routing path in the first set of routing paths, having been defined by adding at least one serpentine pattern to the corresponding routing path in the first set.
In one aspect of the invention, the first set of routing paths is defined by assigning a relatively low priority to the minimum length routing rule, and then executing a routing engine in a first mode that ignores the minimum length routing rules based on the relatively low priority. The modified set of routing paths is then defined by assigning a relatively high priority to the minimum length routing rules, and executing the routing engine in a second mode that considers the minimum length routing rules based on the relatively high priority.
Apparatus for defining circuit routing paths between components on a substrate comprises a database and a routing engine. The database has an entry that includes a start point, an end point, and a set of routing rules. The set of routing rules can include at least one minimum length routing rule. The routing engine accepts the database as input and, based thereon, defines a first routing path from the start point to the end point. The first routing path is defined while ignoring the minimum length routing rule. Then, the routing engine enforces the minimum length routing rule by increasing the length of the first routing path to define a modified routing path. The apparatus can also include a user interface coupled to the database and the routing engine via which a user can define at least one of the routing rules and at least one of the first or second routing paths.
Other aspects of the present invention are described below.
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patent: 5571996
Fix Robert H.
Tamarkin Vladimir K.
Do Thuan
Smith Matthew
Unisys Corporation
Woodcock Washburn Kurtz Mackiewicz & Norris LLP
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