Printed circuit board layout to minimize the clock delay caused

Details Printed circuit board layout to minimize the clock delay caused Printed circuit board layout to minimize the clock delay caused

1995-10-12

1998-04-21

Kincaid, Kristine L.

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

174250, 174256, 361777, 361748, 361760, 361767, H05K 116

Patent

active

057420092

ABSTRACT:
A printed circuit board layout is provided for minimizing signal delays caused by mismatch in length of the inner leads of a package lead frame. This is accomplished by the provision of a unique conductive trace pattern formed preferably on the top surface or else on a lower surface of an electrically-insulated, heat-conducting printed circuit board. The conductive trace pattern includes a plurality of U-shaped metallized traces. Each of the plurality of U-shaped traces have a varying length so that certain ones adjacent the inner leads at the center of the package lead frame are longer than certain ones adjacent the inner leads at the corners of the package lead frame. The conductive trace pattern and the outer leads of the package lead frame also serve to transfer heat away from a molded-plastic body encapsulating an integrated-circuit die and the package lead frame and distribute the same on the printed circuit board.

REFERENCES:
patent: 5428505 (1995-06-01), Sakemi et al.

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