Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
2002-05-30
2004-08-24
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S680000, C257S779000, C257S780000, C257S737000
Reexamination Certificate
active
06781220
ABSTRACT:
FIELD OF INVENTION
The invention relates to semiconductor memory devices, and in particular, to connection between a memory chip and an external circuit.
RELATED APPLICATIONS
This application claims the benefit of the May 30, 2001 filing date of German application 101 26 310.4-34, the contents of which are herein incorporated by reference.
BACKGROUND
It is known to provide semiconductor memory devices which comprise a memory chip and a printed circuit board device for connecting the memory chip to an external circuit. The memory chip has an integrated circuit formed with the aid of a lithography method. In order to be able to address the memory chip, memory chip pads or bond in a pads are provided on the memory chip. The printed circuit board device is provided in order to be able to connect the memory chip to an external circuit. The printed circuit board device comprises printed circuit board pads or lead fingers for connecting the printed circuit board device to the memory chip by means of a bonding wire, which is generally formed as a fine gold wire. At the two longitudinal sides of the printed circuit board device, a multiplicity of contacts are provided in order to contact-connect and connect the printed circuit board device to the external circuit. Since the memory chip has a much smaller size than the printed circuit board device and thus the entire semiconductor memory device, the ratio of memory chip size to semiconductor memory device size is relatively small. For many applications, the size of the semiconductor memory device is of great importance; in particular, it is desirable to maximize the ratio of memory chip size to semiconductor memory device size. Furthermore, if such a memory is operated with high clock rates (e.g. 300 MHz), problems can arise during the data transmission on account of the high clock rate.
SUMMARY
Consequently, the object of the present invention is to provide a printed circuit board device, the use thereof and a semiconductor memory device which have a better ratio of memory chip size to semiconductor memory device size and a which enable a reliable operation of a memory chip in particular at high clock rates.
The invention provides a printed circuit board device (so-called interposer) for a semiconductor memory device for connecting a memory chip to an external circuit, the printed circuit board device comprising:
a multiplicity of printed circuit board pads (so-called lead fingers) for connecting the printed circuit board device to the memory chip, the printed circuit board pads being arranged in at least one column-type arrangement,
a multiplicity of data terminals (so-called DQ and DQS pins) for inputting and outputting data, the data terminals being arranged in at least two column-type arrangements, which preferably run essentially parallel to the arrangement of the printed circuit board pads,
data connections for connecting the data terminals and the printed circuit board pads,
wherein the data connections of the at least two data terminals, which are arranged in the at least two column-type arrangements in a manner provided in different columns, to the respective printed circuit board pads are configured in such a way that their electrical properties and/or the temporal offset (so-called time skew or DQ/DQ skew or DQS/DQS skew) of the respective data signals are essentially identical.
The fact that the data connections to the at least two data terminals have essentially the same electrical properties and/or the same temporal offset makes it possible to ensure that the applied data signals are present essentially simultaneously at the respective data inputs of the memory chip. Consequently, a reliable data transmission can be ensured in particular at high clock rates.
Preferably, the data connections to all the data terminals are configured in such a way that their electrical properties and/or the temporal offset of the respective data signals are essentially identical.
By furthermore providing for all the data connections to have the same electrical properties and/or the same temporal offset it is possible to achieve an even more advantageous operation of the memory chip.
In a preferred embodiment, the data connections are configured in such a way that their physical lengths are essentially identical. The data connections are furthermore preferably configured in such a way that their cross sections are essentially identical.
The provision of data connections having the same length and the same cross section makes it possible to achieve an essentially identical capacitance and inductance of the data connections, which has the result that the data signals are in each case all present simultaneously at the memory chip.
Preferably, the printed circuit board pads are arranged in a central region, most preferably in the longitudinal direction, of the printed circuit board device.
In a preferred embodiment, the printed circuit board device according the invention furthermore comprises addressing terminals (so-called address pins) for inputting address information and addressing connections for connecting the addressing terminals and the printed circuit board pads,
command terminals (so-called command pins) for inputting commands and command connections for connecting the command terminals under printed circuit board pads, and/or
supply terminals (so-called VDD, VSS, VDDQ and VSSQ pins) for the connection of supply voltages and supply connections for connecting the supply terminals and the printed circuit board pads,
wherein in each case a printed circuit board pad is assigned to each data terminal and to each addressing terminal and to each command terminal and at least one printed circuit board pad is assigned to each supply terminal.
The data terminals, the addressing terminals, the command terminals and the supply terminals are further preferably arranged in a grid pattern.
In a preferred embodiment, a plurality of data terminals are arranged in a manner grouped in at least one group in the grid pattern.
Preferably, the data terminals comprise receiver Strobe terminals (so-called DQS pins), which is arranged centrally in the column direction in the group of data terminals.
It has proved to be advantageous to group the data terminals and to order the receiver Strobe terminals centrally in the groups. Clock signals rather than data are transmitted via the receiver Strobe terminals. However, on account of the similarity between the signal waveform of the clock signals and the signal waveform of the data signals, the receiver Strobe terminals are treated as data terminals. This arrangement improves the signal transmission of the individual DQ terminals. Furthermore, the time skew, i.e. the temporal offset of the signals, [lacuna] be reduced.
Preferably, the supply terminals comprise data supply terminals (so-called VDDQ and VSSQ pins), which are arranged in the grid pattern between the data terminals and the printed circuit board pads. Furthermore, at least two printed circuit board pads are assigned to each data supply terminal.
The data processing in the memory chip requires a high current. The latter can be provided by the advantageous arrangement of the data supply terminals, in particular by the arrangement via at least two printed circuit board pads.
Preferably, the supply terminals comprise grounding terminals (so-called VSS pins), which are arranged in the grid pattern in an outer region, preferably in the outermost column-type arrangement.
The grounding terminals are further preferably arranged in the vicinity of the data terminals. The connections of the grounding terminals preferably in each case run between two “rows” of the data terminals arranged in a column-like manner, whereby advantageous shielding of the data terminals can be achieved.
In a preferred embodiment, on the printed circuit board device, at positions corresponding to the data terminals, the addressing terminals, the command terminals and the supply terminals, fixing facilities, preferably small tin balls (so-called BGA balls), are furthermore provid
Dortu Jean-Marc
Feurle Robert
Schmölz Paul
Täube Andreas
Fish & Richardson P.C.
Infineon - Technologies AG
Thai Luan
LandOfFree
Printed circuit board for semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Printed circuit board for semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Printed circuit board for semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3309077