Preventing erroneous operation in a system where...

Details Preventing erroneous operation in a system where... Preventing erroneous operation in a system where...

2009-08-21

2011-11-29

Ismail, Shawki S (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

C713S375000, C713S502000

Reexamination Certificate

active

08067955

ABSTRACT:
This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention senses the multiple ready signals and waits until all the finite state machines generate the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.

REFERENCES:
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patent: 6122690 (2000-09-01), Nannetti et al.
patent: 6981082 (2005-12-01), Ho et al.
patent: 7941660 (2011-05-01), Lu et al.
patent: 2007/0101043 (2007-05-01), Herman

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