Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-08-28
2001-03-27
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S725000, C438S945000, C438S626000, C430S313000, C430S317000
Reexamination Certificate
active
06207546
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of preventing etching damage to a passivation layer in the fabrication of integrated circuits, and more particularly, to a method of preventing etching damage to a passivation layer by crosslinking a negative resist in the manufacture of integrated circuits.
(2) Description of the Prior Art
The manufacture of integrated circuit devices has progressed to the point where half micron and sub-half micron feature sizes are common. In this technology, the top metal spacing becomes narrow enough so that keyholes are formed within the silicon oxide/silicon nitride layers covering the metal lines for certain geometrical patterns, such as at the turning points of a group of parallel metal lines.
For example,
FIG. 1
illustrates a semiconductor substrate
10
. Layer
14
contains various semiconductor device structures and insulating layers, not shown. The topmost metal layer
20
is shown overlying layer
14
. Typically, the metal layer is passivated by first depositing a layer of silicon oxide
22
by plasma enhanced chemical vapor deposition (PECVD). Then, a silicon nitride layer
24
is deposited also by PECVD. Because the gap between the metal lines is so small, a keyhole
25
can form within the gap.
After the passivation layer has been deposited, a layer of photoresist is coated over the passivation layer and the layer is patterned as desired. However, when the photoresist
30
is coated over a layer containing keyholes, the resist will flow into the keyholes resulting in a thinner resist layer in these areas, as shown in FIG.
2
. During the plasma etching process, a portion of the photoresist mask will be eroded away. Because of the thinner resist in the areas of the keyholes, the passivation layer in those areas may be exposed by the eroding of the photoresist causing damage in the device areas.
After the etching step, the photoresist mask is stripped. This is typically done by a wet strip followed by O
2
plasma ashing. As illustrated in
FIG. 3
, the photoresist
31
within the keyhole may harden so that it cannot be removed by the photoresist strip. Wet chemicals
33
from the wet strip may be trapped around the hardened photoresist
31
. Hard baking both before and during the plasma etch and O
2
plasma etching all are performed at high temperatures which can cause the resist to harden.
The wafer is then annealed in hydrogen and nitrogen at between about 400 to 450° C. This alloy process provides H
2
at a relatively high temperature to react with the silicon dangling bonds to stabilize the SiO
2
—Si interface. The alloy process is used to release trapped interface charges from the plasma processes, including etching, depositing, and ashing. During this annealing, the hardened photoresist
31
may be extruded from the keyhole. The wet chemicals
33
previously trapped by the photoresist
31
would evaporate and cause defects to the device.
The most common solution to this problem is to planarize the passivation layer by covering it with a spin-on-glass layer or a silicon oxide layer deposited by subatmospheric chemical vapor deposition (SACVD) and then etching back. Then, the photoresist is coated onto the planarized layer. However, this method changes the passivation film structure requiring further device reliability qualification and dramatically increased production costs.
U.S. Pat. No. 5,494,853 to Lur discloses a method of metal patterning, including metal islands and dummy vias, that will prevent openings to tunnels and holes within a passivation layer and thereby prevent a photoresist coating from sinking into the holes. U.S. Pat. No. 5,007,234 to Scoopo et al teaches a planarization process utilizing three resist layers. U.S. Pat. No. 4,794,021 to Potter discloses a photoresist reflow technique to form a uniform thick photoresist coating. A much less complicated and costly method for solving the resist thinning problem over keyholes is desired.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming a passivation layer in the manufacture of an integrated circuit device.
A further object of the invention is to provide a method for preventing passivation damage caused by keyholes in the fabrication of integrated circuits.
A still further object of the invention is to provide a method for preventing passivation keyhole damage and resist extrusion in the fabrication of integrated circuits.
Yet another object is to provide a method for preventing passivation keyholes damage and resist extrusion by a resist crosslinking mechanism.
In accordance with the objects of this invention a new method of preventing passivation keyhole damage and resist extrusion by a resist crosslinking mechanism is achieved. Semiconductor device structures are formed in and on a semiconductor substrate and covered by an insulating layer. Metal lines are formed overlying the insulating layer wherein there is a gap between two of the metal lines. A passivation layer is deposited overlying the metal lines. A negative tone photoresist material is coated over the passivation layer. The photoresist is exposed to light through a mask wherein the mask is clear overlying the metal lines in an active area and wherein the mask is opaque overlying a metal line in a bonding pad area where a bonding pad is to be formed. The portion of the negative tone photoresist underlying the clear mask is exposed to light whereby crosslinks are formed within the exposed photoresist and wherein the portion of the photoresist underlying the opaque mask is unexposed. The photoresist is developed wherein the unexposed photoresist is removed leaving the exposed photoresist as an etching mask. The passivation layer is etched away where it is not covered by the etching mask where the bonding pad is to be formed wherein the crosslinked photoresist protects the underlying passivation layer from etching damage.
REFERENCES:
patent: 4649099 (1987-03-01), Oguchi
patent: 4794021 (1988-12-01), Potter
patent: 5077234 (1991-12-01), Scoopo et al.
patent: 5494853 (1996-02-01), Lur
patent: 5506173 (1996-04-01), Nishimoto
Chen Shih-Shiung
King Mingchu
Ackerman Stephen B.
Everhart Caridad
Pike Rosemary L.S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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