Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-04-23
2002-09-10
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S113000, C711S170000, C710S036000
Reexamination Certificate
active
06449697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method, system, and program for prestaging data into cache from a storage system in preparation for data transfer operations.
2. Description of the Related Art
Data prestaging techniques are used to prestage data from a non-volatile storage device, such as one or more hard disk drives, to a high speed memory, such as a volatile memory device referred to as a cache, in anticipation of future data requests. The data requests may then be serviced from the high speed cache instead of the storage device which takes longer to access. In this way, data may be returned to the requesting device faster.
During a sequential read operation, an application program, such as a batch program, will process numerous data records stored at contiguous locations in the storage device. It is desirable during such sequential read operations to prestage the sequential data into cache in anticipation of the requests from the application program. Present techniques used to prestage sequential blocks of data include sequential caching algorithms systems, such as those described in the commonly assigned patent entitled “CACHE DASD Sequential Staging and Method,” having U.S. Pat. No. 5,426,761. A sequential caching algorithm detects when a device is requesting data as part of a sequential access operation. Upon making such a detection, the storage controller will begin prestaging sequential data records following the last requested data record into cache in anticipation of future sequential accesses. The cached records may then be returned to the application performing the sequential data operations at speeds substantially faster than retrieving the records from a non-volatile storage device.
Another prestaging technique includes specifying a block of contiguous data records to prestage into cache in anticipation of a sequential data request. For instance, the Small Computer System Interface (SCSI) provides a prefetch command, PRE-FETCH, that specifies a logical block address where the prestaging operation begins and a transfer length of contiguous logical blocks of data to transfer to cache. The SCSI PRE-FETCH command is described in the publication “Information Technology-Small Computer System Interface-2,” published by ANSI on Apr. 19, 1996, reference no. X3.131-199x, Revision 10L, which publication is incorporated herein by reference in its entirety.
Both these techniques for prestaging data records in anticipation of sequential operations are not useful for data records that have a logical sequential relationship but are stored at non-contiguous or dispersed physical locations in the storage device. Such prior art prestaging techniques are intended for sequential operations accessing data records stored at contiguous physical locations. For instance, the sequential detection algorithms and SCSI PRE-FETCH command do not prestage non-contiguous blocks. If the sequential detection algorithms and the SCSI PRE-FETCH command are used to prestage a range of data records including both the non-contiguously stored data records that are needed, then they will also prestage data records that the application program does not need. The above techniques waste processor cycles and cache storage space by prestaging data records that will not be requested. Thus, current prestaging techniques do not provide an optimal solution for prestaging non-contiguous tracks into cache.
Thus, there is a need in the art for improved prestaging techniques.
SUMMARY OF THE PREFERRED EMBODIMENTS
To overcome the limitations in the prior art described above, preferred embodiments disclose a method, system, and program for prestaging data into cache from a storage system in preparation for data transfer operations. A first processing unit communicates data transfer operations to a second processing unit that controls access to the storage system. The first processing unit determines addressable locations in the storage system of data to prestage into cache and generates a data structure capable of indicating contiguous and non-contiguous addressable locations in the storage system including the data to prestage into the cache. The first processing unit transmits a prestage command and the data structure to the second processing unit. The prestage command causes the second processing unit to prestage into cache the data at the addressable locations indicated in the data structure. The first processing unit then requests data at the addressable locations indicated in the data structure. In response, the second processing unit returns the requested data from the cache.
In alternative embodiments, the storage system storage space is logically divided into multiple tracks, wherein each track includes one or more data records. Each data record includes an index area providing index information on the content of the data record and a user data area including user data. The addressable locations indicated in the data structure comprise tracks in the storage system including the data records to prestage into the cache. In such embodiments, the data structure indicates addressable locations in the storage system including the data to prestage into the cache.
In yet further embodiments, the data structure comprises a bit map data structure having bit map values for addressable locations in the storage system. Bit map values of one in the data structure indicate corresponding addressable locations including the data to prestage into cache.
In still further embodiments, the addressable locations in the data structure correspond to data having a logical sequential ordering within the first processing unit.
In further instances, the addressable locations in the storage system including the data having the logical sequential ordering are at non-contiguous addressable locations in the storage system.
Preferred embodiments thus provide a mechanism to prestage data into cache using a data structure indicating addressable locations to prestage in a range of addressable locations. Preferred embodiments are particularly applicable to situations where an application program performs a sequential operation to process data records according to a logical sequential ordering. However, such data records having the logical sequential ordering may be stored at non-contiguous physical locations on a storage device. In such case, the data structure of the preferred embodiments can cause another processing unit, such as a storage controller that controls access to the storage system, to prestage into cache the data having a logical sequential relationship, yet stored at non-contiguous physical locations in the storage device. In this way, when the application program requests the data having the logical sequential ordering during sequential processing, the storage controller can return the requested data directly from cache. Returning the data from cache is substantially faster than retrieving the requested data from non-contiguous physical locations from the storage device.
Preferred embodiments thus improve system performance for application programs performing sequential operations on data logically ordered yet stored at non-contiguous physical location by prestaging the logically ordered data into a high-speed cache.
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Beardsley Brent Cameron
Berger Jeffrey Allen
Bataille Pierre Michel
International Business Machines - Corporation
Kim Matthew
Konrad Raynes & Victor & Mann LLP
Victor David W.
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