Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-09-15
2000-04-11
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711156, 711 3, 711202, 711209, G06F 1200
Patent
active
060498528
ABSTRACT:
A means for preserve cache consistency is provided for a system comprising a central processing unit, a first physical memory, a second physical memory for which the address is common to the first physical memory in at least some duplicated address range of the entire physical address, a cache memory, and a memory controller, wherein the first or second physical memory is selected depending on the operation mode. Flag bits are provided in a tag memory of the cache for information identifying the data source. The cache then does not determine a cache hit/miss only based on whether data related to a CPU requested address exists in the cache, but determines whether the source of data requested by the CPU is consistent with the source of data stored in the cache by taking into account information on the operation mode simultaneously sent from the CPU. A cache hit is determined only when such two conditions are met.
REFERENCES:
patent: 4158227 (1979-06-01), Baxter et al.
patent: 4484267 (1984-11-01), Fletcher
patent: 4885680 (1989-12-01), Anthony et al.
patent: 5038278 (1991-08-01), Stelly, Jr. et al.
patent: 5155826 (1992-10-01), Fadem
patent: 5265232 (1993-11-01), Gannon
patent: 5276888 (1994-01-01), Kardach et al.
patent: 5339437 (1994-08-01), Yuen
patent: 5357628 (1994-10-01), Yuen
patent: 5475829 (1995-12-01), Thome
patent: 5491806 (1996-02-01), Horstmann et al.
patent: 5509139 (1996-04-01), Ayash et al.
patent: 5544344 (1996-08-01), Frame
patent: 5574877 (1996-11-01), Dixit et al.
patent: 5577221 (1996-11-01), Liu et al.
patent: 5579503 (1996-11-01), Osborne
patent: 5603011 (1997-02-01), Piazza
patent: 5630147 (1997-05-01), Datta et al.
patent: 5636363 (1997-06-01), Bourekas et al.
patent: 5638532 (1997-06-01), Frame et al.
patent: 5668968 (1997-09-01), Wu
patent: 5675763 (1997-10-01), Mogul
patent: 5745770 (1998-04-01), Thangadurai et al.
John Goodman, "Memory Management for all of us," Deluxe Edition Sams Publishing, Div of Prentice Hall Computer Pub, First Edition, pp. 239-254, pp. 670-675 and Reference Card (2 pages), 1993.
Nakada Takeo
Oba Nobuyuki
Sho Ikuo
Chan Eddie P.
International Business Machines - Corporation
Kim Hong
McKinley Martin J.
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