Prescaler architecture capable of non integer division

Details Prescaler architecture capable of non integer division Prescaler architecture capable of non integer division

2006-03-07

2006-03-07

Lee, Thomas C. (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C331S002000, C327S115000

Reexamination Certificate

active

07010714

ABSTRACT:
A prescaler generally comprising a first circuit, a multiplexer, and a second circuit. The first circuit may be configured to present a plurality of control signals in response to a first clock signal having a first frequency. The multiplexer may be configured to multiplex a plurality of data signals in response to the control signals to present a second clock signal having a second frequency that is a non-integer fraction of the first frequency. The second circuit may be configured to present the data signals in response to the second clock signal.

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Ahola et al, A 4 GHz CMOS Multiple Module Prescaler, 1998, IEEE, pp. 323-326.

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