Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing
Reexamination Certificate
1999-12-31
2003-09-30
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Addressing
C345S539000, C711S206000
Reexamination Certificate
active
06628294
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to memory address formation in computers and digital processing systems, and more specifically, to translating virtually addressed display data.
BACKGROUND INFORMATION
Electronic products may be thought of as those products that involve the controlled conduction of electrons or other charge carriers, especially through microprocessors. Examples of electronic products include televisions, computers, work stations, and servers as well as those involved in high-end networking and storage technology. Just about all electronic products employ one or more microprocessors disposed within the platform of a chip located on a printed circuit board. These microprocessors engage a computer operating system as well as applications. The central processing unit within the platform interacts with a memory controller to run the computer operating system and the applications.
A monitor may be viewed as a device connected to an electronic product's video output that permits a user to interact with the central processing unit through visual images. The visual images that are presented on a computer monitor to a computer user generally include display streams of data and overlay streams of data. An electronic gun may be swept rapidly back and forth across the screen of a monitor to activate individual pixels of the screen according to the data stream. This data is known to the engine of the electronic gun at its virtual memory address but is stored in the physical memory of the platform at a physical memory address.
To make use of this data, the platform operating system employs a Memory Management Unit (MMU) during its startup sequence to translate virtual addresses into physical addresses and store that translation in buffers of a translation table. A Translation Look-aside Buffer (TLB) as used in a virtual memory system may be viewed as including a table that lists the physical address page number associated with each virtual address page number. The TLB may also store each translation to a cache with tags that are based on virtual addresses. The virtual address may be presented simultaneously to the TLB and to the cache so that cache access and the virtual-to-physical address translation can proceed in parallel (the translation is done “on the side”).
When a request for data located at a physical address arrives in the TLB from a graphics engine, the request is described by its virtual address. Based on the request, the TLB accesses either the stored or cached virtual to physical address translation. If the requested address is not cached, the TLB controller fetches the new translation from memory such that the physical memory address may be used to locate the data in main memory.
Latency is the time from when a display engine requests data from a streamer until the display engine receives the data and displays it on a monitor. It takes a period of time to request and receive the translation and then to fetch and receive the physical data. For video display streams (referred to as isochronous data streams) employing display and overlay streamers, there is a strict time requirement within which the display engine must receive the requested data. Translation fetch in response to a data request adds time to the graphic display process. A problem of adding time to the graphic display process is that if the data does not arrive by the time the electronic gun is at a pixel located at a position on the monitor, the electronic gun will not properly update the pixel, so that image corruption such as screen tearing results.
One technique to account for the latency is to increase the buffer space inside the chip. This increases the number of virtual to physical translations that may be performed during the startup sequence. Although this reduces the time from when the request is initially made for data by the engine to the time that the data is needed by the engine, this increases the gate count so as to require a bigger die. This, in turn, increases the cost of the chip.
SUMMARY OF THE INVENTION
A method according to an embodiment of the invention includes fetching address translations for a current group of scanlines of image data and prefetching address translations for a next group of scanlines of image data. The prefetching occurs while the current group of scanlines of image data is being rendered on a display. The current group of scanlines and the next group of scanlines are the same size such that determining address translations for the next group of scanlines terminates at or before the time the current group of scanlines have been rendered on the display.
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Sadowsky Jonathan B.
Sreenivas Aditya
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tung Kee M.
LandOfFree
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