Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-07-24
2007-07-24
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S103000, C711S104000, C711S105000, C711S167000
Reexamination Certificate
active
10916298
ABSTRACT:
A method and apparatus is provided for prefetching in a data processing system (10). The data processing system (10) has a bus master (14) and a memory controller (16) coupled to a bus (12). A memory (18) is coupled to the memory controller (16). In the data processing system (14) an address is driven onto the bus (12). Before the address is qualified, data corresponding to the address is prefetched. Prefetching the data before the address is qualified allows prefetches to be accomplished sooner.
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Moyer William C.
Shaw Craig D.
Bragdon Reginald
Chiu Joanna G.
Freescale Semiconductor Inc.
Hill Daniel D.
Ruiz Aracelis
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